Fab Tool Biz Faces Challenges In 2015

By Mark LaPedus - 11 Dec, 2014 - Comments: 0

After a slight downturn in 2013, the semiconductor equipment industry rebounded and experienced a solid upturn in 2014. The recovery was primarily driven by tool spending in the foundry and [getkc id="93" kc_name="DRAM"]sectors. Another big and ongoing story continued to unfold in 2014. In late 2013, [getentity id="22817" e_name="Applied Materials"] announced a definitive agreement to acquir... » read more

One-On-One: Mark Bohr

By Mark LaPedus - 18 Sep, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss process technology, transistor trends, chip-packaging and other topics with Mark Bohr, a senior fellow and director of process architecture and integration at Intel. SE: Intel recently introduced chips based on its new 14nm process. Can you briefly describe the 14nm process? Bohr: It’s our second-generation, tri-gate technology. So it has al... » read more

Different Approaches Emerge For Stacking Die

By Ed Sperling - 21 Aug, 2014 - Comments: 1

The concept of stacking die to shorten wires, improve performance, and reduce the amount of energy required to drive signals has been in research for at least the past dozen years at both IBM and Intel. And depending upon whom you ask, it could be another 2 to 10 years before it becomes a mainstream packaging approach—if it happens at all. At least part of the confusion stems from how you ... » read more

Wireless 3D Stacking

By Barry Pangrle - 18 Aug, 2014 - Comments: 2

Hot Chips 26 wrapped up this week and there were many interesting presentations. One of the many presentations that caught my attention was given by Dave Ditzel, CEO of ThruChip, and is titled, “Low-Cost 3D Chip Stacking with ThruChip Wireless.” The technology is as it sounds — a wireless communication path for stacked die. The first question you may be asking is, ‘Why would anyone w... » read more

What’s Next For Memory?

By Mark LaPedus - 14 Aug, 2014 - Comments: 4

Apple, Samsung and others are developing the next wave of smartphones and tablets. OEMs want to integrate new memory schemes that provide more bandwidth at lower power. But there are some challenges in the arena that are prompting memory makers to rethink their mobile DRAM roadmaps. The conventional wisdom was that memory makers would ship mobile DRAMs based on the new LPDDR4 interface stand... » read more

When Will 2.5D Cut Costs?

By Brian Bailey - 07 Aug, 2014 - Comments: 2

There is a constant drive to reduce costs within the semiconductor industry and, up until now, [getkc id="74" comment="Moore's Law"] provided an easy path to enable this. By adopting each smaller node, transistors were cheaper, but that is no longer the case, as explained in a recent article. The industry will need to find new technologies to make this happen and some people are looking towards... » read more

Manufacturing Bits: June 24

By Mark LaPedus - 24 Jun, 2014 - Comments: 0

A cup of sub-wavelength images The National Institute of Standards and Technology (NIST) and the University of Michigan have developed a technology that could enable sub-wavelength images at radio frequencies. Researchers used a mere glass cup, and laser light at optical wavelengths, to measure and image RF fields. In the future, this technology could measure the behavior of metamaterials. ... » read more

Executive Insight: CH Wu

By Ed Sperling - 21 Apr, 2014 - Comments: 0

Semiconductor Engineering sat down with CH Wu, president and CEO of Advantest Taiwan, to talk about business, politics, and his philosophy on what really motivates people. What follows are excerpts of that conversation. SE: Tell us a little about who you are and your background. Wu: I graduated from college with a degree in electrical engineering and started at Philips Electric, then moved ... » read more

Time To Revisit 2.5D And 3D

By Mark LaPedus - 17 Apr, 2014 - Comments: 2

Chipmakers are reaching various and challenging inflection points. In logic, many IC makers face a daunting transition from planar transistors at 20nm to finFETs at 14nm. And on another front, the industry is nearing the memory bandwidth wall. So perhaps it’s time to look at new alternatives. In fact, chipmakers are taking a hard look, or re-examining, one alternative—stacked 2.5D/3D chi... » read more

Challenges In 3D Resists

By Katherine Derbyshire - 24 Mar, 2014 - Comments: 2

3D integration straddles the line between CMOS fabs and packaging and assembly houses. Depending on the structure being fabricated, the most appropriate process might be more “CMOS-like” or more “package-like.” For example, in CMOS fabs lithography means spin-on photoresist, exposed by a high precision stepper. Inherent in this approach is an assumption that the wafer surface is flat... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.