Chip Industry Technical Paper Roundup: Apr. 29


New technical papers recently added to Semiconductor Engineering’s library: [table id=424 /] Find more semiconductor research papers here. » read more

Chip Industry Week in Review


To listen to the podcast version, click here. TSMC unveiled an unusually detailed roadmap at this week's North America Technology Symposium, including future architectures for 3D-ICs for high-performance computing and small, extremely low-power chips for AR/VR glasses, and two implementations of system-on-wafer. Fig. 1: TSMC's future packaging and stacking roadmap. Source: TSMC The ... » read more

Hardware Security: Assessment Method For Attacks Using Real-World Cases (TU Wien, TÜV Austria)


A new technical paper titled "The Pains of Hardware Security: An Assessment Model of Real-World Hardware Security Attacks" was published by researchers at TU Wien and TÜV Austria. "We review some of the publicly known HW attacks that have occurred and propose an assessment scheme for the attacks and the defense on hardware," states the paper. Find the technical paper here. April 2025. ... » read more

Chip Industry Week In Review


Intel said its new fab in Licking County, Ohio will be delayed due to financial struggles and a need to align chip production with market demand, reported the Columbus Dispatch. Construction is now estimated to be completed in 2030, with operations to start in 2030 or 2031. The company said it already has invested $3.7 billion locally. Apple plans to invest more than $500 billion in the U.S... » read more

Research Bits: Feb. 18


Predicting band gap with neural networks Researchers from Kyoto University developed a machine learning model to predict the band gap of novel semiconductor materials. Using data from almost 2,000 semiconductor materials, the team tested six different neural networks. They found that the incorporation of conditional generative adversarial networks (CGAN) and message passing neural networks ... » read more

Chip Industry Technical Paper Roundup: Feb. 18


New technical papers recently added to Semiconductor Engineering’s library: [table id=406 /] Find all technical papers here. » read more

Simulation Study Of Vertically Stacked 2D NSFETs


A new technical paper titled "Simulation of Vertically Stacked 2-D Nanosheet FETs" was published by researchers at Università di Pisa and TU Wien. Abstract "We present a simulation study of vertically stacked 2-D nanosheet field-effect transistors (NSFETs). The aim of this investigation is to assess the performance and potential of FinFET alternatives, i.e., gate-all-around (GAA) nanosheet... » read more

Chip Industry Week In Review


The new Trump administration was quick to put a different stamp on the tech world: President Trump rescinded a long list of Biden’s executive orders, including those aimed at AI safety and the mandate for 50% EVs by 2030. Roughly 1.3 million EVs were sold in the U.S. in 2024, up 7.3% from 2023. The new administration announced $500 billion ($100 billion initially) in private sector in... » read more

Schottky Barrier Transistors: Status, Challenges and Modeling Tools


A technical paper titled "Roadmap for Schottky barrier transistors" was published by researchers at University of Surrey, Namlab gGmbH, Forschungszentrum Jülich (FZJ), et al. Abstract "In this roadmap we consider the status and challenges of technologies that use the properties of a rectifying metal-semiconductor interface, known as a Schottky barrier (SB), as an asset for device functio... » read more

Chip Industry Technical Paper Roundup: Nov. 25


New technical papers recently added to Semiconductor Engineering’s library: [table id=386 /] » read more

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