tag: UC Berkeley

RISC-V Pros And Cons
By Ann Mutschler - 29 May, 2017 - Comments: 7

Simpler, faster, lower-power hardware with a free, open, simple instruction set architecture? While it sounds too good to be true, efforts are underway to do just that with RISC-V, the instruction-set architecture (ISA) developed by UC Berkeley engineers and now administered by a foundation. It has been known for some time that with [getkc id="74" comment="Moore's Law"] not offering the same... » read more

Speeding Up Neural Networks
By Ed Sperling - 27 Apr, 2017 - Comments: 2

Neural networking is gaining traction as the best way of collecting and moving critical data from the physical world and processing it in the digital world. Now the question is how to speed up this whole process. But it isn't a straightforward engineering challenge. Neural networking itself is in a state of almost constant flux and development, which makes it something of a moving target. Th... » read more

System Bits: March 14
By Ann Mutschler - 14 Mar, 2017 - Comments: 0

Neuromorphic computing While for five decades, Moore’s law held up pretty well, today, transistors and other electronic components are so small they’re beginning to bump up against fundamental physical limits on their size, and because Moore’s law has reached its end, it’s going to take something different to meet the need for computing that is ever faster, cheaper and more efficient. ... » read more

What Does An AI Chip Look Like?
By Ed Sperling - 01 Mar, 2017 - Comments: 5

Depending upon your point of reference, artificial intelligence will be the next big thing or it will play a major role in all of the next big things. This explains the frenzy of activity in this sector over the past 18 months. Big companies are paying billions of dollars to acquire startup companies, and even more for R&D. In addition, governments around the globe are pouring additional... » read more

MEMS: A Tale Of Two Tough Markets
By Ed Sperling - 22 Feb, 2017 - Comments: 0

The MEMS market is growing rapidly, profits not so much. In most market segments, this would be a signal that more automation and standardization are required. But in the microelectromechanical systems world, fixes aren't so simple. And even where something can be automated, that automation doesn't work all the time. In fact, while MEMS devices are extremely difficult to design, build and ma... » read more

Battling Fab Cycle Times
By Mark LaPedus - 16 Feb, 2017 - Comments: 9

The shift from planar devices to finFETs enables chipmakers to scale their processes and devices from 16nm/14nm and beyond, but the industry faces several challenges at each node. Cost and technical issues are the obvious challenges. In addition, cycle time—a key but less publicized part of the chip-scaling equation—also is increasing at every turn, creating more angst for chipmakers and... » read more

System Bits: Dec. 20
By Ann Mutschler - 20 Dec, 2016 - Comments: 0

Removing quasiparticles from superconducting quantum circuits improves lifetime Given that an important prerequisite for the realization of high-performance quantum computers is that the stored data should remain intact for as long as possible, an international team of scientists at European interdisciplinary research institute Forschungszentrum Jülich has succeeded in making further improvem... » read more

System Bits: Dec. 13
By Ann Mutschler - 13 Dec, 2016 - Comments: 0

Data, code sharing standards for computational studies While reporting new research results involves detailed descriptions of methods and materials used in an experiment, when a study uses computers to analyze data, create models or simulate things that can’t be tested in a lab, how can other researchers see what steps were taken or potentially reproduce results? To this end, a new report by... » read more

The Limits Of The Lifecycle
By Katherine Derbyshire - 17 Nov, 2016 - Comments: 0

In the first article in my series on sustainability, I cited one estimate that attributed most of the electricity consumed by an integrated circuit to manufacturing, not use. Other analyses, however, come to exactly the opposite conclusion, with above 90% of lifetime energy consumption accounted for by the use phase. How can that be? The glib answer is that industry efforts to build more eff... » read more

Sub-Lithographic Patterning Via Tilted Ion Implantation For Scaling Beyond The 7nm Technology Node
By Technical Paper Link - 10 Nov, 2016 - Comments: 0

Tilted ion implantation (TII) can be used in conjunction with pre-existing masking features on the surface of a substrate to form features with smaller dimensions and smaller pitch. In this paper, the resolution limit of this sub-lithographic patterning approach is examined via experiments as well as Monte Carlo process simulations. TII is shown to be capable of defining features with size belo... » read more

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