tag: UMC

What’s Next In Advanced Packaging
By Mark LaPedus - 20 Jun, 2019 - Comments: 3

Packaging houses are readying the next wave of advanced IC packages, hoping to gain a bigger foothold in the race to develop next-generation chip designs. At a recent event, ASE, Leti/STMicroelectronics, TSMC and others described some of their new and advanced IC packaging technologies, which involve various product categories, such as 2.5D, 3D and fan-out. Some new packaging technologies ar... » read more

Power, Reliability And Security In Packaging
By Ed Sperling - 19 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with Ajay Lalwani, vice president of global manufacturing operations at eSilicon; Vic Kulkarni, vice president and chief strategist in the office of the CTO at ANSYS; Calvin Cheung, vice president of engineering at ASE; Walter Ng, vice president of business management at UMC; and Tien Shiah, senior manager for memory at Samsun... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 07 Jun, 2019 - Comments: 0

Market research IC Insights has released its forecast for chips in terms of applications. Communications is still the biggest IC market, but automotive is growing the fastest. In its first forecast of artificial intelligence (AI) edge processors, International Data Corp. (IDC) estimates that worldwide shipments of AI-optimized processors for edge systems will reach 340.1 million units in 20... » read more

Week In Review: Design, Low Power
By Jesse Allen - 17 May, 2019 - Comments: 0

Tools & IP Cadence introduced the Tensilica Vision Q7 DSP, which provides up to 1.82 TOPS and is specifically optimized for simultaneous localization and mapping (SLAM). The DSP has a very long instruction word (VLIW) SIMD architecture, an enhanced instruction set supporting 8/16/32-bit data types and optional VFPU support for single and half precision, and a number of iDMA enhancements in... » read more

Challenges In Making And Testing STT-MRAM
By Mark LaPedus - 07 May, 2019 - Comments: 1

Several chipmakers are ramping up a next-generation memory type called STT-MRAM, but there are still an assortment of manufacturing and test challenges for current and future devices. STT-MRAM, or spin-transfer torque MRAM, is attractive and gaining steam because it combines the attributes of several conventional memory types in a single device. In the works for years, STT-MRAM features the ... » read more

Focus Shifting From 2.5D To Fan-Outs For Lower Cost
By Ed Sperling - 29 Apr, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with Calvin Cheung, vice president of engineering at ASE; Walter Ng, vice president of business management at UMC; Ajay Lalwani, vice president of global manufacturing operations at eSilicon; Vic Kulkarni, vice president and chief strategist in the office of the CTO at ANSYS; and Tien Shiah, senior manager for memory at Samsung. W... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 26 Apr, 2019 - Comments: 0

Fab tools and test Lam Research has developed a new self-maintaining or self-cleaning chamber for its etch tools. With the technology, Lam announced a new industry benchmark has been set for productivity in etch processing using its self-maintaining equipment. Etch process modules are typically cleaned weekly or monthly. Recently, Lam and a chipmaker reached the milestone of going 365 days... » read more

Electric Cars Gain Traction, But Challenges Remain
By Mark LaPedus - 22 Apr, 2019 - Comments: 4

Battery-powered electric vehicles are expected to reach a milestone in terms of shipments in 2019, but the technology faces several significant hurdles to gain wider adoption in the market. Limited driving range, high costs, battery issues, and a spotty charging infrastructure are the main challenges for battery electric vehicles (BEVs). In addition, there are issues with various power semic... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 19 Apr, 2019 - Comments: 0

Chipmakers Here comes the battle between 5nm and 6nm processes at two foundry vendors—Samsung and TSMC. Meanwhile, Intel is behind and scrambling to get 10nm out the door. (Intel's 10nm is equivalent to 7nm from the foundries.) Last week, TSMC announced delivery of a complete version of its 5nm design infrastructure. TSMC’s 5nm technology is based on a finFET. This week, Samsung anno... » read more

Lithography Options For Next-Gen Devices
By Mark LaPedus - 18 Apr, 2019 - Comments: 2

Chipmakers are ramping up extreme ultraviolet (EUV) lithography for advanced logic at 7nm and/or 5nm, but EUV isn’t the only lithographic option on the table. For some time, the industry has been working on an assortment of other next-generation lithography technologies, including a new version of EUV. Each technology is different and aimed at different applications. Some are here today, w... » read more

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