Chip Industry’s Technical Paper Roundup: July 5


New technical papers recently added to Semiconductor Engineering’s library: [table id=114 /] (more…) » read more

Leveraging Large Language Models (LLMs) To Perform SW-HW Co-Design


A technical paper titled “On the Viability of using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Accelerators” was published by researchers at University of Notre Dame. Abstract: "Deep Neural Networks (DNNs) have demonstrated impressive performance across a wide range of tasks. However, deploying DNNs on edge devices poses significant challenges due to stringent power and com... » read more

Rethinking Engineering Education In The U.S.


The CHIPS Act, as well as the ongoing need for talent, is causing both industry and academia in America to rethink engineering education, resulting in new approaches and stronger partnerships. As an example, Arizona State University (ASU) now has a Secure, Trusted, and Assured Microelectronics Center (STAM). The center offers an interdisciplinary approach to learning secure and trusted semic... » read more

Chip Industry’s Technical Paper Roundup: Nov. 15


New technical papers added to Semiconductor Engineering’s library this week. [table id=63 /] » read more

Multi-Bit In-Memory Computing System for HDC using FeFETs, Achieving SW-Equivalent-Accuracies


A new technical paper titled "Achieving software-equivalent accuracy for hyperdimensional computing with ferroelectric-based in-memory computing" by researchers at University of Notre Dame, Fraunhofer Institute for Photonic Microsystems, University of California Irvine, and Technische Universität Dresden. "We present a multi-bit IMC system for HDC using ferroelectric field-effect transistor... » read more

Technical Paper Round-Up: Aug 23


New technical papers added to Semiconductor Engineering’s library this week. [table id=46 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit for... » read more

Efficient Neuromorphic AI Chip: “NeuroRRAM”


New technical paper titled "A compute-in-memory chip based on resistive random-access memory" was published by a team of international researchers at Stanford, UCSD, University of Pittsburgh, University of Notre Dame and Tsinghua University. The paper's abstract states "by co-optimizing across all hierarchies of the design from algorithms and architecture to circuits and devices, we present ... » read more

Cryogenic CMOS Becomes Cool


Cryogenic CMOS is a technology on the cusp, promising higher performance and lower power with no change in fabrication technology. The question now is whether it becomes viable and mainstream. Technologies often appear to be just on the horizon, not quite making it, but never too far out of sight. That's usually because some issue plagues it, and the incentive is not big enough to solve the ... » read more

Week In Review, Manufacturing, Test


Post-CHIPS Act Micron is discussing a potential new fab that could employ thousands of workers, following the passage of the Chips and Science Act. Idaho is hoping it will be built near its headquarters facilities in Boise, but Micron hasn’t committed publicly. Rob Beard, senior vice president, general counsel and corporate secretary at Micron, told the Idaho Statesman the company is consi... » read more

Technical Paper Round-up: May 31


New technical papers added to Semiconductor Engineering’s library this week. [table id=30 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit for... » read more

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