tag: UVM

Analog’s Day Of Reckoning
By Brian Bailey - 16 Jun, 2015 - Comments: 0

The numbers being touted by the semiconductor industry for IoT edge devices are staggering. How they are going to be used, who will make them, or indeed who will make money from them are much less certain. The industry seems to be clear about the content of these devices. A small processor, some flash memory or possibly even some of the new memory technologies that are coming along, a radio ... » read more

Layering Protocol Verification
By Synopsys - 22 Apr, 2015 - Comments: 0

Layering protocols are modeled using layering structures that mirror the protocol layers. There are significant challenges in modelling verification components for layering protocols such as (1) reuse, (2) scalability, (3) controllability, and (4)observability. Furthermore, there may be requirements for complex test scenarios where a great deal of interaction is required between test sequence e... » read more

The Week In Review: Design/IoT
By Jesse Allen - 06 Mar, 2015 - Comments: 0

Mergers & Acqusitions Mentor Graphics acquired Tanner EDA, bolstering their position in tools for analog, mixed-signal and MEMs. Terms of the deal were not disclosed. NXP joins forces with Freescale. The merger carries a $16.7 billion price tag and potentially creates a new leader in the automotive and MCU markets. Standards Accellera sent UVM 1.2 off to the IEEE P1800.2 working... » read more

Blog Review: Jan. 7
By Ed Sperling - 07 Jan, 2015 - Comments: 0

Ansys' Justin Nescott has extracted the top 5 engineering technology articles for 2014. Check out the turbocharged Dyson hand vac and the suspended animation trials. Mentor's J. VanDomelen looks at on-demand additive manufacturing on the International Space Station, otherwise known as 3D modeling and printing. It's a lot faster than waiting for a delivery. Cadence's Brian Fuller sits dow... » read more

Industry Scorecard For 2014
By Brian Bailey - 22 Dec, 2014 - Comments: 0

At the end of last year, Semiconductor Engineering asked the industry about the developments they expected to see in 2014. If you care to refresh your memory, they were categorized under markets, semiconductors and development tools. Now it is time to look back and see how accurate those predictions were and where they fell short. Part one addressed the market and semiconductor areas and in thi... » read more

Top-Down SoC Verification
By Frank Schirrmeister - 18 Dec, 2014 - Comments: 0

In the world of system-on-chip (SoC) verification, 2014 was an interesting year of transition. After much discussion throughout the year about graph-based techniques and the role of software for verification, we at Cadence ended the year with a bang – last week we announced Perspec System Verifier. The customers with whom we’ve been working on this product for years tell us that this is a b... » read more

Hybrid Verification: The Only Way Forward
By Brian Bailey - 01 Dec, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the state of the industry for [getkc id="10" kc_name=" functional verification"]. The inability of RTL [getkc id="11" kc_name="simulation"] to keep up with verification needs is causing rapid change in the industry. Taking part in the discussion are Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphics"]; Janick Bergeron, fe... » read more

Blog Review: June 18
By Ed Sperling - 18 Jun, 2014 - Comments: 1

Mentor’s Vern Wnek recalls “a living hell” of being trapped in a small office for three weeks with a PCB designer who ate too much garlic and sweated profusely. This could be a reality TV series. What do engineers really think about UVM? Cadence's Richard Goering braved a 7 a.m. breakfast at DAC to hear a panel of experts, including reps from Intel, Ericsson, Imagination and Freescale,... » read more

Is Formal Ready To Displace Simulation?
By Brian Bailey - 21 May, 2014 - Comments: 2

In part one of this roundtable, the panelists talked about the recent changes that have brought formal to the forefront of verification and discussed the challenges that the UVM have brought to formal. In part two, the panel focused on the subject of coverage and the ways in which formal coverage can be combined with simulation. In this segment we start exploring the impact that sequential equi... » read more

How To Improve Debug Productivity
By Ann Mutschler - 24 Apr, 2014 - Comments: 0

In the realm of SoC verification world, it often takes a very short amount of time to write the testbench and the code, and the rest of the time — up to 90% — is spent debugging. After all, verification is essentially finding the bugs in a design. Debugging essentially has evolved over the years on the same path and complexity curve as design. Now debugging needs to evolve to keep pace, ... » read more

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