Verification As A Flow (Part 1)

By Brian Bailey - 05 Jul, 2018 - Comments: 2

Semiconductor Engineering sat down to discuss the transformation of verification from a tool to a flow with Vladislav Palfy, global manager application engineering for OneSpin Solutions; Dave Kelf, chief marketing officer for Breker Verification Systems; Mark Olen, product marketing group manager for Mentor, A Siemens Business; Larry Melling, product management director, System & Verificati... » read more

Get Ready For Verification 3.0

By Brian Bailey - 24 May, 2018 - Comments: 0

Jim Hogan, managing partner of Vista Ventures, LLC, is perhaps the best-known investor in the EDA space. Recently, he has been focusing time and attention on verification startups, including cloud technology company Metrics, and Portable Stimulus pioneer Breker Verification Systems. This adds to his longer-term commitment to formal verification with OneSpin Solutions. These companies are part ... » read more

Inside UVM, Take Three

By Vatsal Choksi - 26 Apr, 2018 - Comments: 0

The reason why UVM came up with such phases is because synchronization among all design-testbench was necessary. Using Verilog and VHDL, verification engineers did not have facilities such as clocking block or run phases. Now, it is very important that the time at which test vectors applied from test-bench reaches the Design Under Test(DUT) at the same time. If timing for different signals vari... » read more

Going Deep Or Broad With Formal?

By Ann Mutschler - 28 Mar, 2018 - Comments: 0

Whether to apply [getkc id="33" comment="formal verification"] technology to semiconductor design broadly or deeply is a tough question. It hinges on what is the best way to achieve maximum ROI. Do you want to identify hard to find bugs, and get a certain level of confidence about a block? Where should the effort be placed? Is it by going deep, meaning a team of specialists or experts must b... » read more

Executive Insight: Wally Rhines (March 2018)

By Brian Bailey - 01 Mar, 2018 - Comments: 0

Wally Rhines, president and CEO of [getentity id="22017" e_name="Mentor, a Siemens Business"], sat down with Semiconductor Engineering to discuss a wide range of industry and technology changes and how that will play out over the next few years. What follows are excerpts of that conversation. SE: What will happen in the end markets? Rhines: The end markets are perhaps more exciting from a... » read more

Inside UVM, Take Two

By Vatsal Choksi - 22 Feb, 2018 - Comments: 0

In this blog, my major focus is on explaining the concepts such as Sequence, Sequencer, Driver and showing how the communication takes place from sequence to sequencer and from sequencer to driver. In the previous blog, I included a top-level diagram of the UVM structure, showing different base classes. So, let’s look at the main concepts and follow the communication mechanism they use for... » read more

Using Data Mining Differently

By Ann Mutschler - 22 Feb, 2018 - Comments: 0

The semiconductor industry generates a tremendous quantity of data, but until very recently engineers had to sort through it on their own to spot patterns, trends and aberrations. That's beginning to change as chipmakers develop their own solutions or partner with others to effectively mine this data. Adding some structure and automation around all of this data is long overdue. Data mining h... » read more

Blog Review: Jan. 31

By Jesse Allen - 31 Jan, 2018 - Comments: 0

Cadence's Paul McLellan looks back at where TSMC was 30 years ago and the founding philosophy that made the foundry and fabless model work. In a video, Mentor's Colin Walls considers how to make the simplest possible multitasking scheduler with a one line RTOS. Synopsys' Sandeep Taneja checks out the technology behind airbags in cars and the role of the Motorola Serial Peripheral Interfac... » read more

DVCon Committee Picks

By Brian Bailey - 25 Jan, 2018 - Comments: 0

A typical development team contains more verification engineers than design engineers, and that skew is getting wider. You can expect the trend to increase given that verification teams are now getting loaded with added complexity from heterogeneous multi-core systems, functional safety, neural networks and security-in addition to increasing size. Companies that do not keep up with the lates... » read more

Predictions: Methodologies And Tools

By Brian Bailey - 25 Jan, 2018 - Comments: 0

Predictions are divided into four posts this year. Part one covered markets and drivers. The second part looked at manufacturing, devices and companies and this part will cover methodologies and tools. In addition, the outlook from EDA executives will be provided in a separate post. Intellectual property As designs get larger, it should be no surprise that the size of the [getkc id="43" kc_... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

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3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

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Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

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Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

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