tag: verification

Verification Planning And Requirement Tracking For Analog Design
By Mentor, a Siemens Business - 24 Sep, 2014 - Comments: 0

Verifying designs to meet all specifications across all process corners has become an intractable problem from the perspective of debugging, managing, tracking, and meeting verification goals. Implementing a CDV methodology for analog designs can evolve analog design and verification to a standard process-based method that can be tracked and its progress measured. This paper aims to extend comm... » read more

Extending Power Analysis To The Emulation of Complex SoCs
By Jim Kenney - 11 Sep, 2014 - Comments: 0

Using hardware emulation to estimate SoC power consumption delivers significant value. Emulators are capable of long runs on large designs, making it practical to emulate an RTOS boot sequence or graphics processing of multiple frames. Estimating power consumption of these advanced functions executing across the complete SoC provides valuable insight into the chip’s power draw and its impact ... » read more

Transaction Debug
By Synopsys - 21 Aug, 2014 - Comments: 0

SoC design is complex. It involves both software and hardware design that calls for a higher level of abstraction to ensure accurate verification. Transaction-level verification and debug offers this higher abstraction, while staying close to actual hardware signals. Traditionally, its use has been limited by the lack of a better mechanism and database to capture the critical information needed... » read more

Blog Review: Aug. 20
By Ed Sperling - 20 Aug, 2014 - Comments: 0

Ansys’ Bill Vandermark highlights the top five engineering articles of the week. Check out the “Sprouting Baby Monitor.” This may be a sign of what the IoT is really good for. You can also use your cat (or dog or even your kids) to hack your neighbor’s Wi-Fi. Cadence’s Richard Goering says gaps may be narrowing between available tools and what’s needed for 3D-IC design. Now all w... » read more

Signoff Intensity On The Rise
By The SE Staff - 15 Aug, 2014 - Comments: 2

By Ann Steffora Mutschler and Ed Sperling Lithography and signoff are crossing swords at 16/14nm and 10nm, creating new problems that raise questions about just how confident design teams will be when they sign off before tapeout — and how many respins are likely to follow. While designs at 20nm, 16nm and 14nm typically rely on colorless double patterning, at 10nm colors are mandatory. ... » read more

IP/SoC Verification With Assertions
By Larry Vivolo - 07 Aug, 2014 - Comments: 1

There's been a lot of excitement here in Silicon Valley these past weeks with the opening of the new 49ers stadium. I've always found it amazing to see how so many complex, fundamentally different technologies — mechanical, electrical, HVAC, plumbing, audiovisual, food catering, etc. — can be put together to create a functioning ballpark. It all but takes a mastermind to bring all these eng... » read more

The Agony Of Hardware-Assisted Development Choices
By Frank Schirrmeister - 24 Jul, 2014 - Comments: 0

“When defining a product, if you haven’t upset at least one part of the organization, then the product is probably ill defined and tries to address too many things!” That’s what one of my mentors taught me early on in my career as product manager. Ever since then I have been interested in portfolio management. The most recent announcement that we made on the Protium Rapid Prototyping Pl... » read more

Accellera Updates UVM Standard
By Ed Sperling - 01 Jul, 2014 - Comments: 2

Accellera uncorked its backward-compatible UVM 1.2 standard, which fixes dozens of bugs, including sequences for run-time phasing and support for multithreading. “We’ve solved more than a dozen incompatibilities and improved overall productivity,” said Intel’s Thomas Alsop, who serves as co-chair of the UVM (Universal Verification Methodology) working group. “This is a major releas... » read more

Where Do We Stand With CDC?
By Ann Mutschler - 26 Jun, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss where the industry stands on clock domain crossing with Charlie Janac, CEO of Arteris; Shaker Sarwary, VP of Formal Verification Products at Atrenta; Pranav Ashar, CTO at Real Intent; and Namit Gupta, CAE, Verification Group at Synopsys. What follows are excerpts of that conversation. SE: While not a new aspect of design, clock domain crossing is... » read more

New Uses For Emulation
By Ed Sperling - 16 Jun, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss the changing emulation landscape with Jim Kenney, director of marketing for emulation at Mentor Graphics; Tom Borgstrom, director of the verification group at Synopsys; Frank Schirrmeister, group director of product marketing for the System Development Suite at Cadence; Gary Smith, chief analyst at Gary Smith EDA; and Lauro Rizzatti, a verification ... » read more

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