tag: verification

How Mature Are Verification Methodologies?
By Brian Bailey - 14 Sep, 2022 - Comments: 0

Semiconductor Engineering sat down to discuss differences between hardware and software verification and changes and challenges facing the chip industry, with Larry Lapides, vice president of sales for Imperas Software; Mike Thompson, director of engineering for the verification task group at OpenHW; Paul Graykowski, technical marketing manager for Arteris IP; Shantanu Ganguly, vice president o... » read more

New Processor Fuzzing Mechanism
By Technical Paper Link - 07 Sep, 2022 - Comments: 0

Researchers from Boston University and University of Washington published a technical paper titled "ProcessorFuzz: Guiding Processor Fuzzing using Control and Status Registers." Abstract "As the complexity of modern processors has increased over the years, developing effective verification strategies to identify bugs prior to manufacturing has become critical. Undiscovered micro-architectur... » read more

Better, Faster, And More Efficient Verification With The Power Of AI
By Synopsys - 07 Sep, 2022 - Comments: 0

Verification is often the most challenging part of the chip development process. Verification engineers have to balance quality of results (QOR) with time to results (TTR) and cost of results (COR). AI and ML technologies can play a significant part in increasing QOR, speeding up TTR, and reducing COR. This white paper outlines some of the major challenges for verification, describes how AI pro... » read more

Enabling Model-Based Design For DO-254 Certification Compliance
By Siemens EDA - 31 Aug, 2022 - Comments: 0

The increasing prevalence and cost of projects that need to comply with the DO-254 standard is forcing companies to evaluate their development processes. This white paper shows a development approach to compliance using model-based design. It covers how a DO-254 workflow using model-based design promotes a consistent requirements-oriented project view and increases reuse of design and verificat... » read more

The Next Incarnation Of EDA
By Brian Bailey - 25 Aug, 2022 - Comments: 0

The EDA industry has incrementally addressed issues as they arise in the design of electronic systems, but is there about to be a disruption? Academia is certainly seeing that as a possibility, but not all of them see it happening for the same reason. The academic community questioned the future of EDA at the recent Design Automation Conference. Rather than EDA as we know it going away, they... » read more

Learning How To Forget
By Brian Bailey - 25 Aug, 2022 - Comments: 0

There has been a lot of talk recently about the right to be forgotten, or data privacy rights. These require companies that hold data about us to remove it when properly requested. This might be data that was collected as we browse the Internet, or from online shopping. Or perhaps it's collected as we drive our cars past cameras, or GPS tracking of our cellphones, or many other ways – some of... » read more

Verification Scorecard: How Well Is The Industry Doing?
By Brian Bailey - 25 Aug, 2022 - Comments: 0

Semiconductor Engineering sat down to discuss how well verification tools and methodologies have been keeping up with demand, with Larry Lapides, vice president of sales for Imperas Software; Mike Thompson, director of engineering for the verification task group at OpenHW; Paul Graykowski, technical marketing manager for Arteris IP; Shantanu Ganguly, vice president of product marketing at Caden... » read more

Is There A Limit To The Number of Layers In 3D-NAND?
By Karen Heyman - 24 Aug, 2022 - Comments: 1

Memory vendors are racing to add more layers to 3D NAND, a competitive market driven by the explosion in data and the need for higher-capacity solid state drives and faster access time. Micron already is filling orders for 232-layer NAND, and not to be outdone, SK Hynix announced that it will begin volume manufacturing 238-layer 512Gb triple level cell (TLC) 4D NAND in the first half of next... » read more

Formal Verification Methodology For Detecting Security-Critical Bugs in HW & in the HW/Firmware Interface of SoCs (Award Winner)
By Technical Paper Link - 17 Aug, 2022 - Comments: 0

A new technical paper titled "A Formal Approach to Confidentiality Verification in SoCs at the Register Transfer Level" was this year's first place winner of Intel's Hardware Security Academic Award program.   The approach utilizes UPEC (Unique Program Execution Checking) to identify functional design bugs causing confidentiality violations, covering both the processor and its peripherals. ... » read more

Verifying A DDR5 Memory Subsystem
By Siemens EDA - 10 Aug, 2022 - Comments: 0

With the increasing complexity of DDR memory models and a vast set of configurations, it has become a daunting experience for verification engineers to verify memory subsystems. With the help of DDR5 Questa VIP and its unique features, engineers can maximize their debugging capabilities and achieve their verification goals quickly and efficiently. This paper introduces the Siemens EDA DDR5 and ... » read more

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