tag: verification

Growing Complexity Adds To Auto IC Safety Challenges
By Ann Mutschler - 05 Nov, 2020 - Comments: 0

The automotive industry is working to streamline, automate and tame verification of automotive electronic control units, SoCs and other chips used in vehicles, many of which are becoming so complex and intertwined that progress is getting bogged down. Modern cars may have up to 100 ECUs, which control such vehicle functions as engine, powertrain, transmission, brakes, suspension, entertainme... » read more

A Machine Learning-Based Approach To Formality Equivalence Checking
By Avinash Palepu - 29 Oct, 2020 - Comments: 0

By Avinash Palepu, Namrata Shekhar and Paula Neeley After a long and hard week, it is Friday night and you are ready to relax and unwind with a glass of wine, a sumptuous dinner and a great movie. You turn on Netflix and you expect that it will not only have plenty of pertinent suggestions for you, but also the most appropriate one based on all the previous movies and shows that you have wat... » read more

Using Verification Data More Effectively
By Ann Mutschler - 29 Oct, 2020 - Comments: 0

Verification is producing so much data from complex designs that engineering teams need to decide what to keep, how long to keep it, and what they can learn from that data for future projects. Files range from hundreds of megabytes to hundreds of gigabytes, depending on the type of verification task, but the real value may not be obvious unless AI/machine learning algorithms are applied to a... » read more

Solving CSD Verification Challenges
By Ben Whitehead - 29 Oct, 2020 - Comments: 0

To tackle power consumption and slow execution, modern computational storage devices (CSD) seek to reduce data movement by including a small processing element next to the CSD (figure 1). The data request from the host is executed locally by the processing element, data is locally manipulated, and the result sent back to the host. Much less data is exchanged between storage and host, thus savin... » read more

Is Hardware-Assisted Verification Avoidable?
By Brian Bailey - 29 Oct, 2020 - Comments: 1

Emulation is emerging as the tool of choice for complex and large designs, but companies that swap from simulation to emulation increasingly recognize this is not an easy transition. It requires money, time, and effort, and even then not everyone gets it right. Still, there are significant benefits to moving from simulation to emulation, providing these systems can be utilized efficiently en... » read more

Virtual Verification Of Computational Storage Devices
By Mentor, a Siemens Business - 28 Oct, 2020 - Comments: 0

Over recent years, there has been a move to replace hard-disk drive (HDD) storage with solid-state drive (SSD) storage. SDDs are faster, contain no moving parts that can fail or be affected by environmental hazards, and the cost of SSDs has been dropping each year. Unfortunately, the verification of an SSD is quite complex. In particular because of hyperscale datacenter enterprise and client-dr... » read more

Week In Review: Design, Low Power
By Jesse Allen - 16 Oct, 2020 - Comments: 0

Tools & IP Cadence debuted System-Level Verification IP (System VIP), a suite of tools and libraries for automating SoC testbench assembly, bus and CPU traffic generation, cache-coherency validation, and system performance bottleneck analysis. Tests created using the System VIP solution are portable across Cadence simulation, emulation and prototyping engines and can also be extended to po... » read more

Machine Learning Enabled High-Sigma Verification Of Memory Designs
By Nebabie Kebebew - 15 Oct, 2020 - Comments: 0

Emerging applications and the big data explosion have made memory IPs ubiquitous in modern-day electronics. Specifically, the demand for memories with low-die area, low voltage, high capacity, and high performance is rising for use by data center and cloud computing servers. This is essential to serve the exponentially growing connectivity boom and the latest emerging 5G based systems, includin... » read more

Effective Clock Domain Crossing Verification
By Rahul Chirania - 15 Oct, 2020 - Comments: 0

As chips grow ever larger and more complex, gate count and amount of embedded memory grow dramatically. The number of clock domains is also increasing steadily. Several dozen different clocks are common in today’s chips, with some designs having more than a thousand domains. There are several reasons for this explosion: Multiple external interfaces with distinct clock requirements Lic... » read more

Searching For Power Bugs
By Brian Bailey - 15 Oct, 2020 - Comments: 0

How much power is your design meant to consume while performing a particular function? For many designs, getting this right may separate success from failure, but knowing that right number is not as easy as it sounds. Significant gaps remain between what power analysis may predict and what silicon consumes. As fast as known gaps are closed, new challenges and demands are being placed on the ... » read more

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