tag: verification

Everyone’s A System Designer With Heterogeneous Integration
By Ann Mutschler - 02 Oct, 2023 - Comments: 0

The move away from monolithic SoCs to heterogeneous chips and chiplets in a package is accelerating, setting in motion a broad shift in methodologies, collaborations, and design goals that are felt by engineers at every step of the flow, from design through manufacturing. Nearly every engineer is now working or touching some technology, process, or methodology that is new. And they are inter... » read more

Industry Pressure Grows For Simulating Systems Of Systems
By Brian Bailey - 28 Sep, 2023 - Comments: 0

Most complex systems are designed in a top-down manner, but as the amount of electronic content in those systems increases, so does the pressure on the chip industry to provide high-level models and simulation capabilities. Those models either do not exist today, or they exist in isolation. No matter how capable a model or simulator, there never will be one that can do it all. In some cases,... » read more

What Happened To Portable Stimulus?
By Brian Bailey - 28 Sep, 2023 - Comments: 0

In June 2018, Accellera released the initial version of the Portable Test and Stimulus Standard (PSS), a new verification language that was slated to be the first new abstraction defined within EDA for a couple of decades. So what happened to it? Apart from a few updates at DVCon, there appears to be little talk about it today. However, the industry has its head down trying to make it work, ... » read more

What Does Shift Left With Calibre Mean For IC Designers
By Siemens EDA - 27 Sep, 2023 - Comments: 0

Driven by the world’s seemingly insatiable demand for electronics that constantly do more faster, integrated circuit (IC) design companies are continuously seeking ways to profitably deliver products with more functionality, reliability, and performance while reducing time-to-market. To accomplish this, a well-planned shift left strategy can free up critical time and resources in delivery sch... » read more

Formally Verifying Data-Oblivious Behavior In HW Using Standard Property Checking Techniques
By Technical Paper Link - 15 Sep, 2023 - Comments: 0

A technical paper titled “A Scalable Formal Verification Methodology for Data-Oblivious Hardware” was published by researchers at RPTU Kaiserslautern-Landau and Stanford University. Abstract: "The importance of preventing microarchitectural timing side channels in security-critical applications has surged in recent years. Constant-time programming has emerged as a best-practice technique... » read more

High-Quality Silicon With Cloud-Based Verification
By Rob van Blommestein - 15 Sep, 2023 - Comments: 0

New materials, vertically stacked architectures, and angstrom-level process technologies—the complexity of today’s SoCs continues to grow to meet the needs of demanding applications such as AI, autonomous vehicles, and high-performance computing. This trend only places greater pressure on verification, already notorious for being a significant bottleneck in chip development. Design teams... » read more

Patterns And Issues In AI Chip Design
By Ed Sperling - 14 Sep, 2023 - Comments: 2

AI is becoming more than a talking point for chip and system design, taking on increasingly complex tasks that are now competitive requirements in many markets. But the inclusion of AI, along with its machine learning and deep learning subcategories, also has injected widespread confusion and uncertainty into every aspect of electronics. This is partly due to the fact that it touches so many... » read more

Understanding UVM Coverage For RISC-V Processor Designs
By Synopsys - 13 Sep, 2023 - Comments: 0

Attempting to achieve complete RISC-V verification requires multiple methodologies employing a wide range of relevant tools, including: • Coverage driven simulation based on UVM constrained random methods and compliant with the Universal Verification Methodology (UVM) standard • Static and formal property verification • Equivalence checking • Emulation and FPGA based verific... » read more

Synopsys Timing Constraints Manager: Constraint Verification
By Synopsys - 11 Sep, 2023 - Comments: 0

Constraint verification refers to the verification of the contents of an SDC file to flag situations where the specified constraints are either incorrect, or incomplete, both of which, if not addressed, could result in silicon failure. The key to constraint verification is the ability to flag real issues without swamping an engineer with noise: issues that upon designer review result in no chan... » read more

Integration Of S-Parameters For Power Module Verification Into The Engineers’ Design Environment
By Wilfried Wessel - 07 Sep, 2023 - Comments: 0

By Wilfried Wessel (Siemens EDA), Simon Liebetegger (University of Applied Sciences Darmstadt), and Florian Bauer (Siemens EDA) Developing a power module requires enhanced design and verification methods. Currently, multiple iterations are needed to get the design done. Today, design and manufacturing processes are heavily dependent on physical prototypes. The reason for this is the unique s... » read more

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