OneSpin Users Gather in Munich


Even more than most other high-tech companies, EDA vendors rely on their users for many aspects of their success. Of course, customers provide the revenue that fuels the business, but their influence goes far beyond that. Many features in EDA tools, and even entire categories of products, arise from working closely with advanced users. Even before traditional Beta-testing, selected users provid... » read more

Verification Pilgrims Show A Historical Case For DFT


The Mayflower Steps, where the Pilgrims are believed to have embarked on their journey to America, are located in the beautiful Barbican area of Plymouth, a small town in the southwest of England. As the lone American working for Moortec, a British company based in Plymouth, I stood and stared at them this past September. Separated by a few yards of distance but 399 years of history I found my... » read more

Transforming Silicon Bring-Up


Not too long ago, the return of first silicon from the foundry was a nail-biting moment as power was applied to the chip. Today, better verification methodologies, increased use of emulation, and more mature fabrication practices have transformed how teams utilize first silicon. It is about to be transformed again, and there are some interesting possibilities on the horizon. Much of what use... » read more

Developing Robust Finite State Machines Code With Lint Tools


As design size and complexity grows, the design verification effort grows even more. It takes significant amount of time to thoroughly verify complex control logic of a design, which is the key and the most critical component of design functionality. One of the most common design patterns in the control logic design are finite state machines. They could be designed in different styles, state an... » read more

Thoroughly Verifying Complex SoCs


The number of things that can go wrong in complex SoCs targeted at leading-edge applications is staggering, and there is no indication that verifying these chips will function as expected is going to get any easier. Heterogeneous designs developed for leading-edge applications, such as 5G, IoT, automotive and AI, are now complex systems in their own right. But they also need to work in conju... » read more

Optimizing Hardware Faster


Maximillian Odendahl, CEO of Silexica, sat down with Semiconductor Engineering to talk about high-level synthesis and the changing role of this technology. What follows are excerpts of that conversation. SE: What is the direction that high-level synthesis is heading in? Odendahl: The direction hasn’t changed, but in the past HLS was not usable by the software guys. The main push right n... » read more

Portable Stimulus And Digital Twins


It has been a year since Accellera's Portable Test and Stimulus Specification became a standard. Semiconductor Engineering sat down to discuss the impact it has had, and the future direction of it, with  Larry Melling, product management director for Cadence; Tom Fitzpatrick, strategic verification architect for Mentor, a Siemens Business; Tom Anderson, technical marketing consultant for OneSp... » read more

Three Steps To Complete Reset Behavior Verification


By Chris Kwok, Priya Viswanathan, and Ping Yeung Reset architectures are notoriously complex and difficult to verify. Today’s SoCs contain highly complex reset distributions and synchronization circuitry. Often, reset trees can be larger than clock trees and have many of the same potential issues. Verifying that a design can be correctly reset under all modes of operation presents signi... » read more

The Challenge Of Defining Worst Case


Worst case conditions within a chip are impossible to define. But what happens if you missed a corner case that causes chip failure? As the semiconductor market becomes increasingly competitive — startups and systems companies are now competing with established chipmakers — no one can afford to consider theoretical worst cases. Instead, they must intelligently prune the space to make sur... » read more

Power Complexity On The Rise


New chip architectures and custom applications are adding significant challenges to chip design and verification, and the problems are becoming much more complex as low power is added into the mix. Power always has been a consideration in design, but in the past it typically involved different power domains that were either on, off, or in some level of sleep mode. As hardware architectures s... » read more

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