tag: verification

Digital Twins For Hardware/Software Co-Development
By Frank Schirrmeister - 28 Mar, 2019 - Comments: 0

These days it seems like we could play business bingo when watching presentations at conferences, checking off the most keywords mentioned. Hitting the terms AI, ML, IoT, 5G, and edge computing all together almost guarantees your presentation to be a hit. In recent years, the term “digital twin” has gotten a lot of attention. Recent discussions with Brian Bailey and a paper I wrote for GOMA... » read more

Digital Twins Deciphered
By Brian Bailey - 28 Mar, 2019 - Comments: 0

Ever since Siemens acquired Mentor Graphics in 2016, a new phrase has become more common in the semiconductor industry – the digital twin. Exactly what that is, and what impact it will have on the semiconductor industry, is less clear. In fact, many in the industry are scratching their heads over the term. The initial reaction is that the industry has been creating what are now termed digi... » read more

Utilizing More Data To Improve Chip Design
By Ann Mutschler - 28 Mar, 2019 - Comments: 0

Just about every step of the IC tool flow generates some amount of data. But certain steps generate a mind-boggling amount of data, not all of which is of equal value. The challenge is figuring out what's important for which parts of the design flow. That determines what to extract and loop back to engineers, and when that needs to be done in order to improve the reliability of increasingly com... » read more

The Automation Of AI
By Brian Bailey - 28 Mar, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the role that EDA has in automating artificial intelligence and machine learning with Doug Letcher, president and CEO of Metrics; Daniel Hansson, CEO of Verifyter; Harry Foster, chief scientist verification for Mentor, a Siemens Business; Larry Melling, product management director for Cadence; Manish Pandey, Synopsys fellow; and Raik Brinkmann, CEO ... » read more

Delivering Superior Throughput For EDA Verification Workloads
By Cadence - 27 Mar, 2019 - Comments: 0

Perhaps no industry is more competitive than modern electronics manufacturing and chip design. As consumers, we take it for granted that electronic devices continue to get faster, cheaper, and more capable with each generation. From smart watches to industrial controls to electronic heart-rate monitors, electronics manufacturers are challenged to build smarter, more complex devices leveraging s... » read more

Billion-Gate Design Connectivity
By Ed Sperling - 27 Mar, 2019 - Comments: 0

Sasa Stamenkovic, senior field application engineer at OneSpin Solutions, explains how to find and resolve connectivity issues in integrating large numbers of components in very big designs, often at the leading edge nodes and in markets such as AI. » read more

Formal Apps Take The Bias Out Off Functional Verification
By Mentor, a Siemens Business - 27 Mar, 2019 - Comments: 0

The Questa Formal Apps automate common formal analysis tasks, providing a multiple set of tools for formal verification experts and novices alike. Each of these automated tasks are integrated into a holistic, formal analysis workflow that allows you to use what you need when you need it. This paper describes common verification challenges and how specific Questa Formal Apps handle them along wi... » read more

Address Simulation Turn-Around Time Bottlenecks with VCS Fine-Grained Parallelism
By Synopsys - 27 Mar, 2019 - Comments: 0

Non-stop growth in design size and complexity makes it more difficult than ever for verification teams to keep up with project demands and product goals. According to the Synopsys 2017 Global User Survey, “Verification taking longer than planned” is the top reason for tapeout delays, and “Simulation runtime performance” is the top challenge for verification. Since regression test turn-a... » read more

Data-Driven Verification Begins
By Ed Sperling - 27 Mar, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss data-driven verification with Yoshi Watanabe, senior software architect at Cadence; Hanan Moller, systems architect at UltraSoC; Mark Conklin, principal verification engineer at Arm; and Hao Chen, senior design engineer at Intel. What follows are excerpts of that conversation, which was conducted in front of a live audience at DVCon. (L-R) Yosh... » read more

Week In Review: Design, Low Power
By Jesse Allen - 22 Mar, 2019 - Comments: 0

Synopsys announced several new products: a new test family, a physical verification solution, and a software library for neural net SoCs. TestMAX, the new family of test products, includes soft error analysis and X-tolerant logic BIST for automotive test and functional safety requirements. TestMAX enables test through functional high-speed interfaces and supports early validation of DFT logi... » read more

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