tag: verification

Impacts Of Reliability On Power And Performance
By Ann Mutschler - 13 Dec, 2018 - Comments: 0

Making sure a complex system performs as planned, and providing proper access to memories, requires a series of delicate tradeoffs that often were ignored in the past. But with performance improvements increasingly tied to architectures and microarchitectures, rather than just scaling to the next node, approaches such as determinism and different kinds of caching increasingly are becoming criti... » read more

Mitigating Risk Through Verification
By Ann Mutschler - 05 Dec, 2018 - Comments: 0

Verification is all about mitigating risk, and one of the growing issues alongside of increasing complexity and new architectures is coverage. The whole notion of coverage is making sure a chip will work as designed. That requires determining the effectiveness of the simulation tests that stimulate it, and its effectiveness in terms of activating structures of functional behavior and design.... » read more

Formal Signoff
By Ed Sperling - 04 Dec, 2018 - Comments: 0

Xiaolin Chen, senior AE at Synopsys, looks at what’s good enough coverage, what makes one assertion better than another, and where the potential holes are in verification. https://youtu.be/nBtKE0gDHBU » read more

Making Sure A Heterogeneous Design Will Work
By Ed Sperling - 03 Dec, 2018 - Comments: 0

An explosion of various types of processors and localized memories on a chip or in a package is making it much more difficult to verify and test these devices, and to sign off with confidence. In addition to timing and clock domain crossing issues, which are becoming much more difficult to deal with in complex chips, some of the new devices are including AI, machine learning or deep learning... » read more

Week In Review: Design, Low Power
By Jesse Allen - 30 Nov, 2018 - Comments: 0

Tools & IP UltraSoC debuted functional safety-focused Lockstep Monitor, a set of configurable IP blocks that are protocol aware and can be used to cross-check outputs, bus transactions, code execution, and register states between two or more redundant systems. It supports all common lockstep / redundancy architectures, including full dual-redundant lockstep, split/lock, master/checker, and... » read more

Heterogeneous Computing Raises The Bar For Functional Verification
By Raik Brinkmann - 29 Nov, 2018 - Comments: 0

If there’s one thing certain in chip development, it’s that every innovation in architecture or semiconductor technology puts more pressure on the functional verification process. The increase in gate count for each new technology node stresses tool capacity. Every step up in complexity makes it harder to find deep, corner-case bugs. The dramatic growth in SoC designs brings software into p... » read more

Cracking The Mixed-Signal Verification Code
By Satishkumar Balasubramanian - 29 Nov, 2018 - Comments: 0

Rapid digitization in IoT, automotive, industrial, and communication industry segments are fueling semiconductor industry growth. This growth follows the “More than Moore” paradigm, where new design starts are spread across mature to advanced manufacturing nodes based on end-application targets. With this digitalization, data has become the most valuable resource. Mixed-signal designs pl... » read more

Delivering Superior Throughput For EDA Verification Workloads
By Cadence - 28 Nov, 2018 - Comments: 0

Perhaps no industry is more competitive than modern electronics manufacturing and chip design. As consumers, we take it for granted that electronic devices continue to get faster, cheaper, and more capable with each generation. From smart watches to industrial controls to electronic heart-rate monitors, electronics manufacturers are challenged to build smarter, more complex devices leveraging s... » read more

Heterogeneous Computing Verification
By Ed Sperling - 28 Nov, 2018 - Comments: 0

Raik Brinkmann, CEO of OneSpin Solutions, looks at new architectures involving AI and machine learning, what changes in these multi-accelerator, multi-memories designs, and where problems can crop up both in design and verification. https://youtu.be/0Trtfq8_hKg       See other tech talk videos here. » read more

Formal Datapath Verification
By Ed Sperling - 28 Nov, 2018 - Comments: 0

J.T. Longino, formal verification application engineer at Synopsys, drills down into how to achieve confidence in datapath designs by applying formal solvers and methods to data transformation areas of a design rather than the control path areas. https://youtu.be/n1zO3GxEZVI     See other tech talk videos here. » read more

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