Verification As A Flow (Part 2)

By Brian Bailey - 11 Jul, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss the transformation of verification from a tool to a flow with Vladislav Palfy, global manager application engineering for OneSpin Solutions; Dave Kelf, chief marketing officer for Breker Verification Systems; Mark Olen, product marketing group manager for Mentor, A Siemens Business; Larry Melling, product management director, System & Verificati... » read more

Security Holes In Machine Learning And AI

By Ed Sperling - 09 Jul, 2018 - Comments: 0

Machine learning and AI developers are starting to examine the integrity of training data, which in some cases will be used to train millions or even billions of devices. But this is the beginning of what will become a mammoth effort, because today no one is quite sure how that training data can be corrupted, or what to do about it if it is corrupted. Machine learning, deep learning and arti... » read more

Design Reuse Vs. Abstraction

By Ann Mutschler - 05 Jul, 2018 - Comments: 1

Chip designers have been constantly searching for a hardware description language abstraction level higher than RTL for a few decades. But not everyone is moving in that direction, and there appear to be enough options available through design reuse to forestall that shift for many chipmakers. Pushing to new levels of abstraction is frequent topic of discussion in the design world, particula... » read more

Verification As A Flow (Part 1)

By Brian Bailey - 05 Jul, 2018 - Comments: 2

Adding NoCs To FPGA SoCs

By Ann Mutschler - 28 Jun, 2018 - Comments: 0

FPGA SoCs straddle the line between flexibility and performance by combining elements of both FPGAs and ASICs. But as they find a home in more safety- and mission-critical markets, they also are facing some of the same issues as standard SoCs, including the ability to move larger and larger amounts of data quickly throughout an increasingly complex device, and the difficulty in verifying and de... » read more

Raising The Bar On Flat CDC Verification With Hierarchical Data Models

By Ashish Hari - 28 Jun, 2018 - Comments: 0

By Ashish Hari, Aditya Vij, and Ping Yeung Traditionally, clock domain crossing (CDC) verification at the SoC level has relied on flat simulation runs. But flat CDC verification has run out of gas. Largely because of the increase in the number of asynchronous clocks in larger, faster, more complex designs. Flat CDC runs are too performance intensive, time-consuming, and result in high noise.... » read more

Formal Abstraction And Coverage

By Brian Bailey - 28 Jun, 2018 - Comments: 0

For the past three years, Oski Technology has facilitated a gathering of formal verification experts over dinner to discuss the problems and issues that they face. They discuss techniques they have been attempting with formal verification technologies, along with the results they have been achieving. Semiconductor Engineering was there to record that conversation and to condense it into the ... » read more

Comprehensive CDC Verification Using Advanced Hierarchical Data Models

By Mentor, a Siemens Business - 27 Jun, 2018 - Comments: 0

In this paper, we describe the hierarchical data model (HDM), which is a performance efficient alternative to the traditional flat CDC verification flow. The HDM is equivalent to an abstract CDC model of the IP that captures the CDC intent of the block along with its integration rules. It is a generic data model that can be seamlessly re-used across releases and across designs wherever the IP i... » read more

Monday At DAC 2018

By Brian Bailey - 26 Jun, 2018 - Comments: 0

DAC #55 started with rumors flying. Will this be the last DAC as we know it? Is there a huge chasm forming between academia and the industry? Will DAC be able to make it in Las Vegas where there is no local interest? Of course, those who have been in the industry know that this kind of speculation happens every few years, and in the 80s, Las Vegas was a very popular location for DAC. There was ... » read more

Complexity, Reliability And Cost

By Ed Sperling - 14 Jun, 2018 - Comments: 0

Peter Schneider, director of Fraunhofer's Engineering of Adaptive Systems Division, sat down with Semiconductor Engineering to talk about future challenges in complexity, time to market and reliability issues, advanced packaging architectures, and the impact of billions of connected devices. What follows are excerpts of that discussion. SE: What is the biggest challenge you see in the semico... » read more

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Knowledge Centers
Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

tag: verification