Tech Talk: eFPGA Verification

By Ed Sperling - 05 Oct, 2017 - Comments: 0

Chris Pelosi, vice president of hardware engineering at Achronix, explains how to verify an embedded FPGA, and how that compares with verification of discrete FPGAs and ASICs. https://youtu.be/UBLNabLUg9I Related Stories Tech Talk: EFPGA Test How to plan for sufficient coverage for an embedded FPGA and how much it will cost. Embedded FPGAs Going Mainstream? Programmable devices are be... » read more

Getting A Standard Right The First Time

By Brian Bailey - 02 Oct, 2017 - Comments: 3

The development of standards is a tricky balance, especially when going into areas that are nascent. The [getentity id="22863" e_name="Portable Stimulus Standard"] (PSS), being developed within [getentity id="22028" e_name="Accellera"] is one of those. This could be the most important standard since [gettech id="31017" comment="Verilog"] and [gettech id="31040" comment="VHDL"]. And if there ... » read more

Generically Reusable IP No One Uses

By Neil Johnson - 02 Oct, 2017 - Comments: 5

I can’t tell you how many times this line has jumped into my mind over the last couple decades, probably because I lost count sometime in 1998... Manager: “...why do they put a guarantee on the box then?” Tommy: “‘Cause they know all they sold you was a guaranteed piece of s***.” That’s an exchange from the movie Tommy Boy, a classic from my university days. Tommy Callaha... » read more

System Design And Verification Challenges: Are They On- Or Off-Chip?

By Frank Schirrmeister - 28 Sep, 2017 - Comments: 0

What are the next natural items for mobile devices to be integrated? From 2002 to today, previously separate items (like GPS, cameras and keyboards) have been integrated into the phone. They caused a frenzy of integration within systems on chips. Now we have the Internet of Things (IoT) adding a trillion devices to the picture. Which ones are to be integrated, if any? What does all this mean fo... » read more

System Coverage Undefined

By Brian Bailey - 28 Sep, 2017 - Comments: 1

When is a design ready to be taped out? That has been one of the toughest questions to confront every design team, and it's the one verification engineers lose sleep over. Exhaustive [getkc id="56" kc_name="coverage"] has not been possible since the 1980s. Several metrics and methodologies have been defined to help answer the question and to raise confidence that important aspects of a block... » read more

Verifying AI, Machine Learning

By Ed Sperling - 28 Sep, 2017 - Comments: 0

[getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"], sat down to talk about artificial intelligence, machine learning, and neuromorphic chips. What follows are excerpts of that conversation. SE: What's changing in [getkc id="305" kc_name="machine learning"]? Brinkmann: There’s a real push toward computing at the edge. ... » read more

Verification’s Breaking Points

By Ann Mutschler - 28 Sep, 2017 - Comments: 2

Verification efficiency and speed can vary significantly from one design to the next, and that variability is rising alongside growing design complexity. The result is a new level of unpredictability about how much it will cost to complete the verification process, whether it will meet narrow market windows, and whether quality will be traded off to get a chip out on time in the hopes that it c... » read more

Efficient Verification Of Mixed-Signal SerDes IP Using UVM

By Cadence - 27 Sep, 2017 - Comments: 0

Interface IP is an integral part of systems-on-chips (SoC) that include mobile, automotive, or networking applications and are primarily used for transmitting data over a physical medium between a host and device. The mixed-signal nature of the IP makes verification a challenging task, requiring special considerations for digital and analog sections. This paper describes a robust mixed-signal v... » read more

Power Modeling And Analysis

By Brian Bailey - 27 Sep, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss power modeling and analysis with [getperson id="11489" p_name="Drew Wingard"], CTO at [getentity id="22605" e_name="Sonics"]; [getperson id="11763" comment="Tobias Bjerregaard"], CEO at [getentity id="22908" e_name="Teklatech"]; Vic Kulkarni, vice president and chief strategy officer at [getentity id="22021" e_name="Ansys"]; Andy Ladd, CEO of Baum; ... » read more

Using Emulation to Deliver Storage Market Innovations

By Mentor, a Siemens Business - 13 Sep, 2017 - Comments: 0

SSDs have the unique challenges of using NAND flash as a storage medium. As storage technology and use models continue to evolve, so do the verification tools needed to solve today’s challenges. The Veloce emulator is well suited to address these challenges as has been proven by leading storage companies who are using it today in their production environments. To read more, click here. » read more

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