tag: verification

Virtual PCIe Delivers A “Shift Left” In Software-Defined Networking Emulation
By Mentor, a Siemens Business - 12 Apr, 2017 - Comments: 0

This paper reviews both SW and UVM Vector Based Verification (VBV) methodologies and Advanced Vector Based Verification (AVBV) that uses Software Defined Networking (SDN) HW to service PCIe transactions to the DUT. When deploying VBV methodologies, using the Veloce Transactor Library (VTL) family of components is most appropriate for UVM, C++ and SDK testbench methodologies. We explore how V... » read more

A Program Manager’s Guide to Successful Integrated Circuit Verification
By Cadence - 12 Apr, 2017 - Comments: 0

Accurately monitoring progress on complex integrated circuit (IC) designs has become more difficult as the designs have increased in complexity, leading to surprises from backwards-looking reporting and management processes that do not forewarn coming crises. The Cadence Metric-Driven Verification Methodology provides a more uniform and standardized method of reporting progress towards closure ... » read more

Supporting CPUs Plus FPGAs
By Brian Bailey - 11 Apr, 2017 - Comments: 5

While it has been possible to pair a CPU and FPGA for quite some time, two things have changed recently. First, the industry has reduced the latency of the connection between them and second, we now appear to have the killer app for this combination. Semiconductor Engineering sat down to discuss these changes and the state of the tool chain to support this combination, with Kent Orthner, system... » read more

Custom Chip Verification Issues Grow
By Ann Mutschler - 29 Mar, 2017 - Comments: 0

With the transition to finFETs, design conditions have grown more intense. They now include a wider PVT range and less headroom. As a result, electronic systems for applications such as mobile, consumer, and automotive increasingly are becoming more difficult to design due to the exacting performance requirements of these applications. This is particularly evident in custom design, including... » read more

When Will It Be Done?
By Ed Sperling - 23 Mar, 2017 - Comments: 0

Design teams have done remarkably well in getting chips out the door on time, despite growing complexity at each new node and an increase in the number of features and IP blocks that need to be integrated into designs. There has been plenty of grumbling, along with dire warnings about the future of Moore's Law and the impact of industry consolidation. The reality, though, is that the volume ... » read more

What Is Portable Stimulus?
By Brian Bailey - 23 Mar, 2017 - Comments: 0

When [getentity id="22028" e_name="Accellera"] first formed the [getentity id="22863" comment="Portable Stimulus Working Group”] and gave it that name, I was highly concerned. I expressed my frustration that the name, while fitting with what most people thought [getkc id="10" kc_name="verification"] is about, does not reflect the true nature of the standard being worked on. In short, it is no... » read more

10 Ways To Skin A Formal Puzzle
By Dave Kelf - 23 Mar, 2017 - Comments: 1

During the holidays, OneSpin issued a challenge to solve the classic Einstein’s Riddle using any formal verification tool. Although this puzzle was meant to be a little holiday fun, its solution required thought and some useful formal techniques applicable in everyday functional verification. We received a broad range of answers from engineers across the globe in different companies, inclu... » read more

Users Talk Back On Standards Process
By Brian Bailey - 23 Mar, 2017 - Comments: 0

One of the major themes of DVCon this year was the standard that currently goes by the name of Portable Stimulus (see related story, Portable Stimulus – The Name Must Change). It is not ready for prime time yet, but there was plenty to hear and learn about the emerging standard, including what users think about it and the standardization process. The panel gave the users the opportunity to vo... » read more

Carving Up Verification
By Ed Sperling - 23 Mar, 2017 - Comments: 0

Anirudh Devgan, executive vice president and general manager of [getentity id="22032" e_name="Cadence's"] System & Verification Group, sat down with Semiconductor Engineering to discuss the evolution of verification. What follows are excerpts of that conversation. SE: What’s changing in [getkc id="10" kc_name="verification"]? Devgan: Parallelism, greater capacity and multiple engine... » read more

VCS Fine-Grained Parallelism Simulation Performance Technology
By Synopsys - 22 Mar, 2017 - Comments: 0

Learn how fine-grained parallelism simulation technology enables delivery of breakthrough parallel simulation performance improvement needed to reduce turn-around time for critical-path tests. » read more

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