tag: verification

High-Quality Silicon With Cloud-Based Verification
By Rob van Blommestein - 15 Sep, 2023 - Comments: 0

New materials, vertically stacked architectures, and angstrom-level process technologies—the complexity of today’s SoCs continues to grow to meet the needs of demanding applications such as AI, autonomous vehicles, and high-performance computing. This trend only places greater pressure on verification, already notorious for being a significant bottleneck in chip development. Design teams... » read more

Patterns And Issues In AI Chip Design
By Ed Sperling - 14 Sep, 2023 - Comments: 2

AI is becoming more than a talking point for chip and system design, taking on increasingly complex tasks that are now competitive requirements in many markets. But the inclusion of AI, along with its machine learning and deep learning subcategories, also has injected widespread confusion and uncertainty into every aspect of electronics. This is partly due to the fact that it touches so many... » read more

Understanding UVM Coverage For RISC-V Processor Designs
By Synopsys - 13 Sep, 2023 - Comments: 0

Attempting to achieve complete RISC-V verification requires multiple methodologies employing a wide range of relevant tools, including: • Coverage driven simulation based on UVM constrained random methods and compliant with the Universal Verification Methodology (UVM) standard • Static and formal property verification • Equivalence checking • Emulation and FPGA based verific... » read more

Synopsys Timing Constraints Manager: Constraint Verification
By Synopsys - 11 Sep, 2023 - Comments: 0

Constraint verification refers to the verification of the contents of an SDC file to flag situations where the specified constraints are either incorrect, or incomplete, both of which, if not addressed, could result in silicon failure. The key to constraint verification is the ability to flag real issues without swamping an engineer with noise: issues that upon designer review result in no chan... » read more

Integration Of S-Parameters For Power Module Verification Into The Engineers’ Design Environment
By Wilfried Wessel - 07 Sep, 2023 - Comments: 0

By Wilfried Wessel (Siemens EDA), Simon Liebetegger (University of Applied Sciences Darmstadt), and Florian Bauer (Siemens EDA) Developing a power module requires enhanced design and verification methods. Currently, multiple iterations are needed to get the design done. Today, design and manufacturing processes are heavily dependent on physical prototypes. The reason for this is the unique s... » read more

An Open-Source Solution To Accelerate Autonomous Vehicle Validation And Verification Research
By Technical Paper Link - 28 Aug, 2023 - Comments: 0

A technical paper titled “PolyVerif: An Open-Source Environment for Autonomous Vehicle Validation and Verification Research Acceleration” was published by researchers at Florida Polytechnic University, Embry-Riddle Aeronautical University, Tallinn University of Technology, and Acclivis Technologies. Abstract: "Validation and Verification (V&V) of Artificial Intelligence (AI) based cyb... » read more

An Open-Source Hardware Design And Specification Language To Improve Productivity And Verification 
By Technical Paper Link - 28 Aug, 2023 - Comments: 0

A technical paper titled “PEak: A Single Source of Truth for Hardware Design and Verification” was published by researchers at Stanford University. Abstract: "Domain-specific languages for hardware can significantly enhance designer productivity, but sometimes at the cost of ease of verification. On the other hand, ISA specification languages are too static to be used during early stage d... » read more

Formally Modeling A Security Monitor For Virtual Machine-Based Confidential Computing Systems (IBM)
By Technical Paper Link - 28 Aug, 2023 - Comments: 0

A technical paper titled “Towards a Formally Verified Security Monitor for VM-based Confidential Computing” was published by researchers at IBM Research and IBM T.J. Watson Research Center. Abstract: "Confidential computing is a key technology for isolating high-assurance applications from the large amounts of untrusted code typical in modern systems. Existing confidential computing syste... » read more

New Concepts Required For Security Verification
By Brian Bailey - 28 Aug, 2023 - Comments: 0

Verification for security requires new practices in both the development and verification flows, but tools and methodologies to enable this are rudimentary today. Flows are becoming more complex, especially when they span multiple development groups. Security is special in that it is pervasive throughout the development process, requiring both positive and negative verification. Positive ver... » read more

Optimizing IC Designs For Real-World Use Cases
By Brian Bailey - 24 Aug, 2023 - Comments: 0

Semiconductor systems are becoming more focused on power, performance, and area for the primary scenarios they are likely to see in real-world applications, but increasingly at the expense of secondary tasks. This is happening at all levels of abstraction and all stages of the design flow. At the highest level, processors are being optimized to run a given set of software. RISC-V is one of t... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy