Tuning Heterogeneous SoCs


It's one thing to pack multiple processor cores into a design, but it is much more difficult to ensure the hardware matches the software's requirements, or that the software optimally uses the hardware. Both the hardware and software teams are now facing these issues, and there are few tools to help them fully understand the problems or to provide solutions. Design teams continue to add more... » read more

Verification Of Low-Power Designs With Portable Stimulus


In a recent blog post, Steve Carlson talked about the use of software-driven tests to support concurrent power and performance analysis. Generation of software-driven tests is one of the key technologies that will be enabled by the upcoming standard from Accellera's Portable Stimulus Working Group (PSWG). Portable stimulus spans functional verification as well as performance validation, so PSWG... » read more

Reflecting Back on 2016: Markets


Anyone can make a prediction, and sometimes the more outlandish they are the more they get noticed. But at the end of the year some people hit the mark while others may have been way off. Many people simply make projections based on the current trajectory of trends, while others look for the potential discontinuities that may lie ahead. Semiconductor Engineering examines the projections made... » read more

The Right Kind Of Fun


A couple of weeks ago I went to see “Together Again At Last…For The Very First Time” by John Cleese and Eric Idle at the Center for the Performing Arts in San Jose. I hope all of you recognize both gentlemen as two members of Monty Python. As you can imagine, it was quite an exciting night. With the audience being Monty Python fanatics, every video clip or skit was received with a lot ... » read more

What “Hamilton – An American Musical” Tickets And Emulation Have In Common


During a recent trip to New York, I managed to see “Hamilton, An American Musical”—despite the running joke about how hard it is to get tickets. The sale of “Hamilton” tickets teaches an interesting lesson about what I would call an “automatic feedback loop of value adjustment”. And believe it or not, it bears some resemblance to how verification users actually choose what engine ... » read more

Formal’s Roadmap


Formal verification has come a long way in the past five years as it focused on narrow tasks within the verification flow. Semiconductor Engineering sat down to discuss that progress, and the future of formal technologies, with [getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"]; Harry Foster, chief verification scientist at [g... » read more

Software Platforms Bridge The Design/Verification Gap For 5G Communications Design


We are entering the third phase of information connectivity, one that will change the use of wireless technology dramatically. The first phase connected homes and businesses through wired telephony and the early internet via dial-up modems. Over the last few decades, the development of communication networks has been superseded by wireless mobile technology connecting people instead of places. ... » read more

Tech Talk: Earlier Software


Malte Doerper, senior manager of product management at Synopsys, talks about the big "shift left" for software, where the problems crop up, and how to save as much as a year of development time with automation and better methodologies.   Related Stories Bridging Hardware And Software The need for concurrent hardware-software design and verification is increasing, but are engine... » read more

Gaps In The Verification Flow


Semiconductor Engineering sat down to discuss the state of the functional verification flow with Stephen Bailey, director of emerging companies at [getentity id="22017" e_name="Mentor Graphics"]; [getperson id="11079" comment="Anupam Bakshi"], CEO of [getentity id="22168" e_name="Agnisys"]; [getperson id="11124" comment="Mike Bartley"], CEO of [getentity id="22868" e_name="Test and Verification... » read more

DVCon Europe: 2 Days Of Verification Presentations To Enthusiastic Attendees


Design verification was on full display last week in Munich, Germany, as DVCon Europe offered two full days of more than 30 sessions. Attendees could choose from 16 tutorials, two panels, three keynotes and 16 technical presentations or wander through a small but active exhibit floor, with exhibitors that included OneSpin. The conference for engineers by engineers is meant to be educational,... » read more

← Older posts Newer posts →