tag: verification

Implementing Fan-Out Wafer-Level Packaging with Mentor Graphics
By Mentor, a Siemens Business - 06 Feb, 2017 - Comments: 0

Fan-out wafer-level packaging (FOWLP) is a new high-density packaging technology that is rapidly gaining popularity. What is it? Who needs it? How do you take advantage of it? What limitations does it have? Learn all about FOWLP and our comprehensive tool integration and support for the design and verification of FOWLP products. To read more, click here. » read more

Formal Verification Takes Safety-Critical Applications For A Drive
By Dave Kelf - 26 Jan, 2017 - Comments: 0

The high reliability of safety-critical chips for automotive applications is a well-known imperative for today’s higher-end cars and as driverless cars move closer to reality. Uber, in fact, is testing autonomous cars in Boston of all places, where aggressive driving reigns supreme and honking the horn is considered an art form. As automotive manufacturers realize that their differentiatio... » read more

Hybrid Simulation Picks Up Steam
By Ann Mutschler - 26 Jan, 2017 - Comments: 0

As electronic products shift from hardware-centric to software-directed, design teams are relying increasingly on a simulation approach that includes multiple engines—and different ways to use those engines—to encompass as much of the system as possible. How engineers go about using these approaches, and even how they define them, varies greatly from one company to the next. Sometimes it... » read more

What Can Go Wrong In Automotive
By Ed Sperling - 25 Jan, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss automotive engineering with Jinesh Jain, supervisor for advanced architectures in Ford’s Research and Innovation Center in Palo Alto; Raed Shatara, market development for automotive infotainment at [getentity id="22331" comment="STMicroelectronics"]; Joe Hupcey, verification product technologist at [getentity id="22017" e_name="Mentor Graphics"]; ... » read more

Multiple Dimensions Of Low-Power Verification With Portable Stimulus
By Tom Anderson - 12 Jan, 2017 - Comments: 0

There is little doubt that designing for low power is one of the biggest challenges for today’s system-on-chip (SoC) devices. The need to minimize power consumption is clear for the vast array of portable electronic devices that we use every day. Consumers expect most of their gadgets to last multiple days before they require recharging, and low-power design is the key to extending battery li... » read more

2017: Manufacturing And Markets
By Brian Bailey - 12 Jan, 2017 - Comments: 0

While the industry is busy chatting about the end of Moore's Law and a maturing of the semiconductor industry, the top minds of many companies are having none of it. A slowdown in one area is just an opportunity, in another and that is reflected in the predictions for this year. As in previous years, Semiconductor Engineering will look back on these predictions at the end of the year to see ... » read more

The Fundamental Power States For UPF Modeling And Power Aware Verification
By Mentor, a Siemens Business - 11 Jan, 2017 - Comments: 0

The IEEE 1801-2015 specifies the new semantics of power states through the ‘add_power_state’ UPF command. This new construct primarily allows incremental refinement of power states for power domains and its associated supply sets. The refinement concepts are actually originated from the fundamental conceptual set of power states termed as indefinite, definite, and deferred power states. In ... » read more

EDA, IP Up 7%
By Ed Sperling - 22 Dec, 2016 - Comments: 0

EDA and IP growth increased to $2.094 billion in Q3, a 7% gain over the $1.958 billion reported for the same period in 2015, according to just released data from the Electronic System Design Alliance Market Statistics Service. All geographic regions reported growth last quarter. So did computer-aided engineering, the largest single category, which grew 5.0% to $666.7 million in Q3, up from $... » read more

Top 7 Verification Trends For 2017—Changes In The Game Of Ecosystems
By Frank Schirrmeister - 22 Dec, 2016 - Comments: 0

As the year 2016 comes to a close, how did my predictions from last year hold up to reality? They were all about horizontal and vertical integration. Spoiler alert—they almost all have moved closer to reality. Going forward into 2017, some of the trends will intensify, but the most interesting trend to watch will be how the game of ecosystems in the areas of mobile, server, and intelligent sy... » read more

FPGA VHDL Verification
By Aldec - 22 Dec, 2016 - Comments: 0

By Espen Tallaksen This is actually possible – and with an average efficiency improvement of 20% to 50% for medium to high complexity FPGAs. Less for data path oriented designs and more for control or protocol oriented designs. At no extra cost. All that is required is that you do your testbench development the same way you do your design. Every single FPGA designer knows that a good to... » read more

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