tag: verification

Addressing The Challenges Of Automotive Motor Control
By Ahmed Eisawy - 14 Jul, 2016 - Comments: 0

By Andrew Talan and Ahmed Eisawy As you leave work today and enter the parking lot, you hit the unlock button on your car remote. Using the power lift to open the hatch back, you put your laptop bag in the back of the car. While seated in the car, you adjust your seat position and bump your driver-side mirror into a new position and then head for home. You probably don’t think much about y... » read more

Mixed-Signal/Low-Power Design
By Jeff Dorsch - 14 Jul, 2016 - Comments: 1

Semiconductor Engineering sat down to discuss mixed-signal/low-power IC design with Phil Matthews, director of engineering at Silicon Labs; Yanning Lu, director of analog IC design at Ambiq Micro; Krishna Balachandran, director of low power solutions marketing at [getentity id="22032" comment="Cadence"]; Geoffrey Ying, director of product marketing, AMS Group, [getentity id="22035" e_name="Syno... » read more

Testbench Acceleration Performance Demystified
By Mentor, a Siemens Business - 13 Jul, 2016 - Comments: 0

Part 2 in a series of papers that demystify the performance of SystemVerilog and UVM testbenches when using an emulator for the purpose of hardware-assisted testbench acceleration. In these three papers, architectural and modeling requirements are described, followed by a recommended systematic approach for maximizing overall testbench acceleration speed-up and achieving your ultimate performan... » read more

Abundant Change Ahead
By Brian Bailey - 06 Jul, 2016 - Comments: 1

There is nobody who would question the amazing ride that semiconductors have been on for the past 50 years. It has been described as the longest running exponential that humankind has ever been a part of—and it is not over yet. Still, the future is very likely to be substantially different from the past. It is almost natural for us to see a trend and assume it will continue. There have bee... » read more

Verification Engine Disconnects
By Ed Sperling - 06 Jul, 2016 - Comments: 0

Moving verification data seamlessly between emulation, simulation, FPGA prototyping and formal verification engines may be possible on paper, but it is proving more difficult to implement in the real world. [getkc id="10" kc_name="Verification"] still consumes the most time and money in the design process. And while the amount of time spent on verification in complex designs has held relativ... » read more

Executive Insight: Raik Brinkmann
By Ed Sperling - 06 Jul, 2016 - Comments: 0

[getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"], sat down with Semiconductor Engineering to discuss where and why formal verification is gaining traction, and how it fits alongside other verification approaches. What follows are excerpts of that conversation. SE: [getkc id="33" kc_name="Formal"] has been around for a whi... » read more

The UVM Configuration Database
By Henry Chan - 30 Jun, 2016 - Comments: 0

When I want to wear a certain clothing item, I take out it of the closet. When I go shopping, I add those clothes it to my closet and there are now new items for me to pick out in the future. A database works much the same way, a collection of information that is stored and accessed on demand. Take the UVM configuration database for example. It basically acts as a repository so that when the... » read more

Can Verification Meet In The Middle?
By Brian Bailey - 30 Jun, 2016 - Comments: 0

Since the dawn of time for the EDA industry, the classic V diagram has defined the primary design flow. On the left hand side of the V, the design is progressively refined and partitioned into smaller pieces. At the bottom of the V, verification takes over and as you travel up the right-hand side of the V, verification and integration happens until the entire design has been assembled and valid... » read more

Reducing Design Risk With Testbench Acceleration
By Mentor, a Siemens Business - 29 Jun, 2016 - Comments: 0

Part 1 in a series of papers that demystify the performance of SystemVerilog and UVM testbenches when using an emulator for the purpose of hardware-assisted testbench acceleration. In these three papers, architectural and modeling requirements are described, followed by a recommended systematic approach for maximizing overall testbench acceleration speed-up and achieving your ultimate performan... » read more

Achieving 100% Functional Coverage By Operational Assertion-Based Verification
By OneSpin Solutions - 29 Jun, 2016 - Comments: 0

This white paper presents Operational Assertion-Based Verification (ABV), an advanced formal verification methodology resulting in a predictable, small number of high-level assertions capturing the functionality of a design. Operational ABV enables an automatic formal coverage analysis, which identifies holes in verification plans, unverified design functionality as well as errors and omissio... » read more

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