tag: verification

The Making Of A System Architect
By Sundari Mitra - 24 Mar, 2016 - Comments: 0

I mentor young people from the University of Illinois at Urbana-Champaign, where I got my MSEE. When I talk to them, they tell me they’re applying for chip architecture jobs. But when they graduate with their computer science degrees they all get channeled into verification jobs. Why verification jobs rather than architecture jobs? Because they don’t have a feel for the full architecture. T... » read more

An Unsustainable Divide
By Brian Bailey - 24 Mar, 2016 - Comments: 0

One of the great things about attending DVCon, or any other conference for that matter, is the networking. You get to see so many people who are eager to learn, to talk and to share ideas. When this happens, you tend to hear a lot of statements that have to rattle around in your mind for a while before you can start to make sense of them and see if any coherent themes emerge. By themes, I am... » read more

Are Simulation’s Days Numbered?
By Brian Bailey - 24 Mar, 2016 - Comments: 0

In the latest EDAC report, the value of IP surpassed the value of CAE tools for the first time. Verification tools are an important part of establishing confidence in IP blocks and simulation has been the mainstay of that IP verification strategy. But simulation is under increasing pressure, particularly for full-chip and SoC verification, because it has failed to scale. While it still remains ... » read more

How Do Design And Verification Change In The IoT Age?
By Frank Schirrmeister - 24 Mar, 2016 - Comments: 0

Where is the Internet of Things (IoT) on the hype curve? Are expectations too high, or is it really the next big thing? My recent trip to the Design Automation and Test Conference (DATE) in Dresden, Germany, did not give all the answers, but it definitely did shed some light for me on this topic. A very enthusiastic taxi driver took me back 25 years to the Nov. 9, 1989, the time when the Ber... » read more

Reducing Verification Risk With Formal-Based Observation Coverage
By OneSpin Solutions - 23 Mar, 2016 - Comments: 0

An effective measure of verification progress, together with guidance towards design areas remaining untested, requires a precise view of the test coverage achieved. To risk signing off the verification process without understanding the quality of testing raises the specter of post-production device bugs. OneSpin Solution’s patented Quantify technology employs Observation Coverage, which eval... » read more

IP Risk Sharing
By Brian Bailey - 10 Mar, 2016 - Comments: 0

For most people within the semiconductor industry, managing risk involves making the right product decisions that will enable a company to be profitable, and ensuring the product is successfully produced within the necessary time window. In contrast, for products within high-risk areas such as medical and mil/aero, design often proceeds at a slower pace, using proven technologies and adopting l... » read more

Verification Facing Unique Inflection Point
By Brian Bailey - 10 Mar, 2016 - Comments: 0

The Design and Verification Conference and Exhibition (DVCon) attracted more than 1,100 people to San Jose last week, just slightly less than last year. While a lot of focus, and most of the glory, goes to design within semiconductor companies, it is verification where most of the advancements are happening and thus the bigger focus for DVCon. The rate of change in verification and the producti... » read more

Power — Usage Shift Leads to Methodology Shift
By Mentor, a Siemens Business - 09 Mar, 2016 - Comments: 0

Power exploration and accurate power calculation of SoCs in the target application environment is getting executive attention due to the fact that companies are missing market windows because of power issues. This makes system-level power analysis and management a key measurement. Verification solutions that provide accurate power analysis data early are critical to making design decisions that... » read more

Powerful New Standard
By Brian Bailey - 02 Mar, 2016 - Comments: 1

In December 2015, the IEEE released the latest version of the 1801 specification, titled the IEEE standard for design and verification of low-power integrated circuits, but most people know it as UPF or the Unified Power Format. The standard provides a way to specify the power intent associated with a design. With it, a designer can define the various power states of the design and the contexts... » read more

Seeing Debug for What It Is
By Neil Johnson - 29 Feb, 2016 - Comments: 0

Debug is problem solving. For many hardware developers, debug is a purpose. Finding a bug is a victory! Heck, debug can be flat out heroic. I’m sure we can all think back to colleagues that put in a few 80 hour, coffee fueled weeks, with managers peering over both shoulders, to fix an insidious string of bugs that threatened to further demolish a broken schedule and sabotage tape-out. W... » read more

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