tag: verification

EDA, IP Up 7%
By Ed Sperling - 22 Dec, 2016 - Comments: 0

EDA and IP growth increased to $2.094 billion in Q3, a 7% gain over the $1.958 billion reported for the same period in 2015, according to just released data from the Electronic System Design Alliance Market Statistics Service. All geographic regions reported growth last quarter. So did computer-aided engineering, the largest single category, which grew 5.0% to $666.7 million in Q3, up from $... » read more

Top 7 Verification Trends For 2017—Changes In The Game Of Ecosystems
By Frank Schirrmeister - 22 Dec, 2016 - Comments: 0

As the year 2016 comes to a close, how did my predictions from last year hold up to reality? They were all about horizontal and vertical integration. Spoiler alert—they almost all have moved closer to reality. Going forward into 2017, some of the trends will intensify, but the most interesting trend to watch will be how the game of ecosystems in the areas of mobile, server, and intelligent sy... » read more

FPGA VHDL Verification
By Aldec - 22 Dec, 2016 - Comments: 0

By Espen Tallaksen This is actually possible – and with an average efficiency improvement of 20% to 50% for medium to high complexity FPGAs. Less for data path oriented designs and more for control or protocol oriented designs. At no extra cost. All that is required is that you do your testbench development the same way you do your design. Every single FPGA designer knows that a good to... » read more

Reflecting Back On 2016
By Brian Bailey - 22 Dec, 2016 - Comments: 0

Anyone can make a prediction, and sometimes the more outlandish they are the more they get noticed. But at the end of the year some people hit the mark while others may have been way off. Many people simply make projections based on the current trajectory of trends, while others look for the potential discontinuities that may lie ahead. Semiconductor Engineering examines the projections made... » read more

Overcoming The Limits Of Scaling
By Ed Sperling - 14 Dec, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the increasing reliance on architectural choices for improvements in power, performance and area, with [getperson id="11425" comment=" Sundari Mitra"], CEO of [getentity id="22535" comment="NetSpeed Systems"]; Charlie Janac, chairman and CEO of [getentity id="22674" e_name="Arteris"]; [getperson id="11032" comment="Simon Davidmann"] CEO of [getentit... » read more

SRAM Physical Verification With Calibre Pattern Matching
By Mentor, a Siemens Business - 14 Dec, 2016 - Comments: 0

Traditional SRAM verification flows can require significant resources to implement and support, and still miss critical errors that result in manufacturing defects. Using the Calibre Pattern Matching automated pattern-based solution provides accurate results, avoids costly mask re-spins, and is easily updated to add newly developed SRAM IP cells. To read more, click here. » read more

Embedded Software Verification Issues Grow
By Ann Mutschler - 08 Dec, 2016 - Comments: 0

Embedded software is becoming more critical in managing the power and performance of complex designs, but so far there is no consensus about the best way to approach it—and that's creating problems. Even with safety-critical standards such as DO-178C for aerospace and [gettech id="31076" comment="ISO 26262"] for automotive, different groups of tool providers approach software from differen... » read more

Five Pitfalls In PCIe-Based NVMe Controller Verification
By Saurabh Sharma - 08 Dec, 2016 - Comments: 1

Non-Volatile Memory Express (NVMe) is gaining rapidly in mindshare among consumers and vendors. Some industry analysts are forecasting that PCIe-based NVMe will become the dominant storage interface over the next few years. With its high-performance and low-latency characteristics, and its availability for virtually all platforms, NVMe is a game changer. For the first time, storage devices and ... » read more

Tuning Heterogeneous SoCs
By Brian Bailey - 08 Dec, 2016 - Comments: 0

It's one thing to pack multiple processor cores into a design, but it is much more difficult to ensure the hardware matches the software's requirements, or that the software optimally uses the hardware. Both the hardware and software teams are now facing these issues, and there are few tools to help them fully understand the problems or to provide solutions. Design teams continue to add more... » read more

Verification Of Low-Power Designs With Portable Stimulus
By Tom Anderson - 08 Dec, 2016 - Comments: 0

In a recent blog post, Steve Carlson talked about the use of software-driven tests to support concurrent power and performance analysis. Generation of software-driven tests is one of the key technologies that will be enabled by the upcoming standard from Accellera's Portable Stimulus Working Group (PSWG). Portable stimulus spans functional verification as well as performance validation, so PSWG... » read more

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