tag: verification

Is Your IP-Verification Environment Trying To Kill You?
By Larry Vivolo - 15 Jan, 2015 - Comments: 0

I was watching an old episode of The Office the other night. It was the one where a GPS guided the lead characters into a lake. While we've all fallen victim to a GPS gone bad. Most of us are fortunate enough not to trust technology blindly enough to drive into a lake (or in my case, onto the tarmac at Ft. Lauderdale International). Yet, it's surprisingly easy to find parallels in real life whe... » read more

Blog Review: Jan. 7
By Ed Sperling - 07 Jan, 2015 - Comments: 0

Ansys' Justin Nescott has extracted the top 5 engineering technology articles for 2014. Check out the turbocharged Dyson hand vac and the suspended animation trials. Mentor's J. VanDomelen looks at on-demand additive manufacturing on the International Space Station, otherwise known as 3D modeling and printing. It's a lot faster than waiting for a delivery. Cadence's Brian Fuller sits dow... » read more

Software-Driven Verification (Part 2)
By Brian Bailey - 05 Jan, 2015 - Comments: 0

[getkc id="10" comment="Functional Verification"] has been powered by tools that require hardware to look like the kinds of systems that were being designed two decades ago. Those limitations are putting chips at risk and a new approach to the problem is long overdue. Semiconductor Engineering sat down with Frank Schirrmeister, group director, product marketing for System Development Suite at [... » read more

Blog Review: Dec. 31
By Ed Sperling - 31 Dec, 2014 - Comments: 0

Mentor's J. VanDomelen zeroes in on the two most interesting discoveries from the Philae comet landing. So what was that "eerie cyclical clicking" sound? Synopsys' Ray Varghese digs into basic coherent transaction testing for AXI/ACE compliant interconnects. You might want to put on another pot of coffee. Cadence's Brian Fuller offers some deep insights into synthesis, verification and te... » read more

Hybrid Verification: The Only Way Forward
By Brian Bailey - 29 Dec, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the state of the industry for [getkc id="10" kc_name=" functional verification"]. The inability of RTL [getkc id="11" kc_name="simulation"] to keep up with verification needs is causing rapid change in the industry. Taking part in the discussion are Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphics"]; Janick Bergeron, fe... » read more

Industry Scorecard For 2014
By Brian Bailey - 22 Dec, 2014 - Comments: 0

At the end of last year, Semiconductor Engineering asked the industry about the developments they expected to see in 2014. If you care to refresh your memory, they were categorized under markets, semiconductors and development tools. Now it is time to look back and see how accurate those predictions were and where they fell short. Part one addressed the market and semiconductor areas and in thi... » read more

And the Winner is…
By Brian Bailey - 18 Dec, 2014 - Comments: 0

Semiconductor Engineering now has its first full year under its belt, and I have to say it has been an incredible year. Not only did we exceed a million page views in our first year, but we also got started on the Knowledge Center, an endeavor the likes of which has never been attempted in our industry. It is still very young and has a lot of growing up to do, but it is a wonderful start. We wo... » read more

Top-Down SoC Verification
By Frank Schirrmeister - 18 Dec, 2014 - Comments: 0

In the world of system-on-chip (SoC) verification, 2014 was an interesting year of transition. After much discussion throughout the year about graph-based techniques and the role of software for verification, we at Cadence ended the year with a bang – last week we announced Perspec System Verifier. The customers with whom we’ve been working on this product for years tell us that this is a b... » read more

FPGA Verification with Assertions: Why Bother?
By Mentor, a Siemens Business - 17 Dec, 2014 - Comments: 0

This paper provides a practical, easy, step-by- step set of instructions on how to add assertions to your RTL design. By following the simple guidelines provided in this paper you will benefit by cutting simulation debugging time in half, as well as finding very complex bugs that are likely to escape traditional simulation without assertions. To read more, click here. » read more

Hybrid Verification: The Only Way Forward
By Brian Bailey - 15 Dec, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the state of the industry for [getkc id="10" kc_name=" functional verification"]. The inability of RTL [getkc id="11" kc_name="simulation"] to keep up with verification needs is causing rapid change in the industry. Taking part in the discussion are Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphics"]; Janick Bergeron, fe... » read more

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