Power Is Now Every Engineer’s Concern


Every semiconductor engineer by this point recognizes the need to reduce power inside of SoCs and software. What they don't always see, though, is the chain of events those efforts are beginning to set off—unpredictable, difficult to model, and altogether more difficult to contain. There is no doubt that more functionality on mobile devices requires new ways of designing SoCs, including re... » read more

Problems Lurk In SoC Boundaries


Interfaces always have been a problem, because only rarely does anyone have responsibility for them. Responsibilities generally are tied to functional blocks with the prevailing notion that if all blocks do the right thing, they will also behave correctly when brought together. Design teams that believe this eventually find out the fallacy of this assumption. To make matters worse, these are of... » read more

Electronic System Design In 2015: Busting Through Bottlenecks


It’s December, and that means it’s time to review what just happened in electronics design in the hopes that it will help light a path into the New Year. To simplify a year’s work in a global, sophisticated, ever-changing industry, you could say 2014 hinged on to two main tipping points: The marriage of EDA and IP was consummated. The road to the future forked. Let’s look at #1... » read more

Virtual Prototyping Takes Off


Semiconductor Engineering sat down to discuss [getkc id="104" kc_name="virtual prototyping"] with Barry Spotts, senior core competency FAE for fabric and tools at [getentity id="22186" comment="ARM"]; Vasan Karighattam, senior director of architecture for SoC and SSW engineering at [getentity id="22664" e_name="Open-Silicon"]; Tom De Schutter, senior product marketing manager for Virtualizer So... » read more

Real-Time Trace: A Better Way To Debug Embedded Applications


Firmware and application software development is often the critical path for many embedded designs. Problems that appear in the late phases of the development can be extremely difficult to track down and debug, thus putting project schedules at risk. Traditional debug techniques cannot always help to localize the issue. This white paper shows the benefits of debugging with ‘real-time trace’... » read more

Hybrid Verification: The Only Way Forward


Semiconductor Engineering sat down to discuss the state of the industry for [getkc id="10" kc_name=" functional verification"]. The inability of RTL [getkc id="11" kc_name="simulation"] to keep up with verification needs is causing rapid change in the industry. Taking part in the discussion are Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphics"]; Janick Bergeron, fe... » read more

Measuring Verification Accuracy


[getkc id="10" kc_name="Verification"] is the unbounded challenge that continues to confound engineering teams across the globe, who want to know when "enough" is "good enough" to proceed to tapeout. The answer is not straightforward, and it includes more variables than in the past, particularly around power. Harry Foster, chief verification scientist at [getentity id="22017" e_name="Mentor ... » read more

Hybrid Verification: The Only Way Forward


Semiconductor Engineering sat down to discuss the state of the industry for [getkc id="10" kc_name=" functional verification"]. The inability of RTL [getkc id="11" kc_name="simulation"] to keep up with verification needs is causing rapid change in the industry. Taking part in the discussion are Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphics"]; Janick Bergeron, fe... » read more

The Next Big Shift In Verification


We are coming to the end of the year—have you started your Christmas shopping list yet? For us bloggers, it is time for predictions about what the next year will bring in EDA technology. Three core trends will shape 2015—even more closely connected verification engines, innovations in hardware-assisted development, and software as a driver for verification. All three core trends are r... » read more

User Case Study


Whenever more than one clock is employed in an SoC (which is all SoCs), the risk of errors from clock domain crossings (CDC) – signals (or groups of signals) that are generated in one clock domain and consumed in another – is incredibly high. Unfortunately, CDC bugs are nearly impossible to catch with conventional simulations. Thus, all too often they escape into silicon. Debugging them in ... » read more

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