tag: VIP

Can IP Integration Be Automated?
By Ann Mutschler - 24 Sep, 2015 - Comments: 1

What exactly does it mean to automate [getkc id="43" comment="IP"] integration? Ask four people in the industry and you’ll get four different answers. “The key issue is how you can assemble the hardware as quickly as you can out of pre-made pieces of IP,” said Charlie Janac, chairman and CEO of [getentity id="22674" e_name="Arteris"]. To Simon Rance, senior product manager in the ... » read more

Top 15 Integrating Points In The Continuum Of Verification Engines
By Frank Schirrmeister - 30 Jul, 2015 - Comments: 0

The integration game between the different verification engines, dynamic and static, is in full swing. Jim Hogan talked about the dynamic engines that he dubbed “COVE”, and I recently pointed out a very specific adoption of COVE in my review of some customer examples at DAC 2015 in “Use Model Versatility Is Key for Emulation Returns on Investment”. Here are my top 15 integrating poin... » read more

HDMI 2.0 Design And Verification Challenges
By Cadence - 11 Mar, 2015 - Comments: 0

High-Definition Multimedia Interface (HDMI) is an audio/video (A/V) trans- mission protocol, which is omnipresent in consumer electronics, personal computing, and mobile products. Modern-day requirements of big screen resolutions, 3D, and multi-channel/multi-stream audio have pushed display devices to use a completely digital, high-speed transmission media, requiring a multi-layered protocol li... » read more

HDMI 2.0 Design And Verification Challenges
By Various Writers - 21 Nov, 2013 - Comments: 0

HDMI designs face challenges with respect to run time and memory consumption due to the huge size of HDMI frames. Scrambling adds more complexity and designs face synchronization and timing challenges. Similar challenges are faced during the functional verification of systems-on- chip (SoCs) including HDMI interfaces. These challenges can be addressed using HDMI verification IP (VIP). To dow... » read more

Experts At The Table: Debug
By Ed Sperling - 18 Oct, 2013 - Comments: 0

By Ed Sperling Semiconductor Engineering sat down with Galen Blake, senior verification engineer at Altera; Warren Stapleton, senior fellow at Advanced Micro Devices; Stephen Bailey, director of solutions marketing at Mentor Graphics; Michael Sanie, senior director of verification marketing at Synopsys. What follows are excerpts of that conversation. SE: The amount of IP is increasing and i... » read more

The Week In Review: Aug. 12
By Ed Sperling - 12 Aug, 2013 - Comments: 0

By Mark LaPedus Is the sky falling on semi capital spending? “We have seen several 2014 industry demand estimates in the 20%+ range, based on the ramps of FinFET and 3D NAND,” said Weston Twigg, an analyst with Pacific Crest Securities. “We expect Samsung to ramp spending in Q4, but we believe foundry and logic spending will remain soft for several quarters. As a result, we are developin... » read more

The Week In Review: June 21
By Ed Sperling - 21 Jun, 2013 - Comments: 0

By Ed Sperling Mentor Graphics rolled out emulation-ready verification IP for MIPI camera and display-based protocols. The VIP enables stimuli generated by UVM and SystemC-based environments and applies them to a design under test (DUT) running in the emulator. Synopsys introduced a tool for implementing and verifying functional engineering change orders, including matching, visualization ... » read more

VIP: Behind The Velvet Rope
By Ed Sperling - 20 Oct, 2011 - Comments: 0

By Ann Steffora Mutschler Some years ago, as engineering teams began to incorporate more protocols into designs and as those protocols grew in sophistication and complexity in order to deliver additional performance, the verification task grew concurrently. At the same time, the design IP market was growing as complexity drove re-use of components, along with verification components—most com... » read more

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