A Flexible Cluster Tool Simulation Framework With Wafer Batch Dispatching Time Recommendation

By UMC - 19 Dec, 2023 - Comments: 0

The semiconductor manufacturing process consists of multiple steps and is usually time-consuming. Information like the turnaround time of a certain batch of wafers can be very useful for manufacturing engineers. A simulation model of manufacturing process can help predict the performance of manufacturing process efficiently, which is very beneficial to the manufacturing engineers. The simulatio... » read more

Semiconductor Device Manufacturing Process Challenges And Opportunities

By Andreas Bier - 07 Dec, 2023 - Comments: 0

Semiconductor device manufacturing involves a complex series of processes that transform raw materials into finished devices. The process typically involves four major stages: wafer fabrication, wafer testing, assembly or packaging, and final testing. Each stage has its own unique set of challenges and opportunities. The semiconductor device manufacturing process faces several challenges, inclu... » read more

Detection Of Contaminants In Positive And Negative Ion Mode Using In-line SIMS With An Oxygen Primary Ion Beam

By Nova - 09 May, 2023 - Comments: 0

Utilizing Secondary Ion Mass Spectrometry (SIMS) for in-line metrology is a newly emerging method of process control that requires contamination-free measurements, enabling SIMS on product wafers. SIMS measurements of negative ions are usually associated with a Cesium primary ion beam. Unfortunately, when Cesium is present in Silicon, it forms trap states in the Si band gap, which can cause ser... » read more

Hunting For Macro Defects: The Importance Of Bare Wafer Inspection

By Aseem Srivastava - 08 Sep, 2022 - Comments: 0

As logic and memory semiconductor devices approach the limits of Moore’s Law, the requirements for accuracy in layer transfer become increasingly stringent. One leading silicon wafer manufacturer estimates that 50% of epitaxial wafer supply for logic will be on nodes equal to or less than 7nm. This is up approximately 30% from earlier in the decade. To meet the demands of extreme ultraviol... » read more

Power/Performance Bits: June 28

By Jesse Allen - 28 Jun, 2022 - Comments: 0

Making uniform wafers Scientists from the Korea Institute of Machinery & Materials (KIMM) and Nanyang Technological University Singapore (NTU Singapore) propose a technique that combines nanotransfer printing with metal-assisted chemical etching to improve wafer uniformity and increase yield. The researchers used a chemical-free nanotransfer printing technique that transfers gold nanost... » read more

Innovative Dual Mark Design For Alignment Verification And Process Monitoring In Advanced Lithography

By UMC - 21 Jul, 2021 - Comments: 0

Improving on product overlay is one of the key challenges when shrinking technology nodes in semiconductor manufacturing. . . . With smart placement of alignment mark pairs in the X and Y direction, it is possible to determine intra-wafer distortion wafer-by-wafer. Both the measurement and modeled results are applied directly as a feed-forward correction to enable wafer level control. In this p... » read more

Greenfield Projects Needed To Meet Silicon Wafer Demand

By Sungho Yoon - 17 Jun, 2021 - Comments: 0

After logging record shipments in the first quarter of 2021, the silicon wafer industry may need to start greenfield projects as soon as this year to boost capacity over the next two years as market demand and average selling prices continue to improve. One segment hamstrung by a supply shortage is 300mm epitaxial wafers, a shortfall we expect to drive continuing price increases in the comin... » read more

Gradual Rebound Or Slight Dip

By Sungho Yoon - 16 Apr, 2020 - Comments: 0

Uncertainty has gripped the silicon wafer market as the COVID-19 pandemic threatens to upend growth projections for 2020. Declines in both shipments and revenue plagued the silicon wafer market in 2019, a downturn that had given way to optimism for 2020 with rising expectations for normalizing inventory levels, memory market improvements, data center market growth and the 5G market takeoff. ... » read more

Sandia’s Fab Gets An Upgrade

By Nishita Rao - 17 Dec, 2019 - Comments: 0

Sandia National Laboratories just finished updating equipment in its microelectronics fab, marking the completion of the first phase of a 3-year fab upgrade program. The transition from 6-inch to 8-inch wafer sizes will align the Department of Energy national lab with industry standards to ensure easier access to tools, spare parts and raw materials. Sandia is a prestigious member of the... » read more

Intra-Field Stress Impact on Global Wafer Deformation

By Veeco - 14 Aug, 2019 - Comments: 0

One of the contributors to layer-to-layer overlay in today’s chip manufacturing process is wafer distortion due to thin film deposition. Mismatch in the film specific material parameters (e.g., thermal expansion coefficients) may result in process-induced warpage of the wafers at room temperature. When these warped wafers are loaded onto the scanner for the next layer exposure, in-plane disto... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?