Week in Review: IoT, Security, Autos


Products/Services Siemens announced that Mazda Motor adopted the Capital electrical design software suite from Mentor, a Siemens Business, for the design of next-generation automotive electrical systems. Mazda is said to use Capital for model-based generative design for the electrical and electronic systems of the entire vehicle platform. Synopsys will host the 11th annual Codenomi-con USA ... » read more

Week In Review: Manufacturing, Test


Trade wars In recent testimony before a U.S. government panel considering tariffs on $300 billion worth of Chinese goods, SEMI called for the removal of about 30 tariff lines. These items are central to the semiconductor manufacturing process. “SEMI asserts that these tariffs will harm not only companies operating in the U.S., but other companies as well in the semiconductor supply chain... » read more

Week In Review: Design, Low Power


ON Semiconductor completed its $946 million acquisition of Quantenna Communications, a San Jose-based company that specializes in Wi-Fi chips and software. Aldec introduced automatic UVM register generation to its Riviera-PRO verification platform. Riviera-PRO can now accept a CSV file or IP-XACT register description as an input and, working at the Register Abstraction Layer (RAL) of UVM, ou... » read more

Falling Chip Forecasts


It’s time to take a pulse of the semiconductor market amid the memory downturn and trade frictions with China. For some time, the DRAM and NAND markets have been hit hard with falling prices and oversupply. Then, the Trump administration last year slapped tariffs on Chinese goods. China retaliated. And the trade war rages on between the U.S. and China. More recently, the U.S. Department... » read more

3D NAND Race Faces Huge Tech And Cost Challenges


Amid the ongoing memory downturn, 3D NAND suppliers continue to race each other to the next technology generations with several challenges and a possible shakeout ahead. Micron, Samsung, SK Hynix and the Toshiba-Western Digital duo are developing 3D NAND products at the next nodes on the roadmap, but the status of two others, Intel and China’s Yangtze Memory Technologies Co. (YMTC), is les... » read more

The Rapid Rise Of RISC-V


The first RISC-V Summit, which took place last month in Santa Clara, CA, appears to be a watershed for the RISC-V ecosystem. The technology is maturing and the ecosystem is growing fast – and that was reflected in the nature of the presentations and news announcements we saw. The accent has started to move to how the technology will be used in real life. UltraSoC’s announcement of a har... » read more

Week In Review: Design, Low Power


Tools OneSpin unveiled a set of formal apps for development and assessment of RISC-V cores. The RISC-V Integrity Verification Solution formalizes the RISC-V ISA in a set of SystemVerilog Assertions to verify compliance for the ISA is met. It provides a formal bug absence core assessment environment for unbounded proofs and systematic discovery of all hidden instructions or unintended side effe... » read more

5 Top Storylines For NAND Biz


2019 is expected to be a busy, if not difficult, year in the NAND flash memory market. Vendors will continue to ramp up 3D NAND, the successor to traditional 2D or planar NAND. Then, over the last year, prices for NAND have dropped with oversupply in the market. What’s in store in 2019? Vendors are expected to rush out their next-generation products. Then, there is a debate whether the... » read more

December ’18 Startup Funding: Big Rounds As 2018 Ends


During the month of December, 16 startups had private funding rounds of $100 million and up, with half of them in the mobility area. Those 16 rounds totaled $3.2 billion as the year concluded. Before the holidays, the SoftBank Vision Fund invested $500 million in Cambridge Mobile Telematics, provider of the DriveWell platform used by insurers, vehicle fleets, wireless carriers, and others to... » read more

Week In Review: Design, Low Power


RISC-V Western Digital announced big plans for RISC-V with a new open source RISC-V core, an open standard initiative for cache coherent memory over a network, and an open source RISC-V instruction set simulator. The SweRV Core features a 2-way superscalar design with a 32-bit, 9 stage pipeline core. It has clock speeds of up to 1.8Ghz on a 28mm CMOS process technology and will be used in vari... » read more

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