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Week In Review: Design, Low Power

New RISC-V cores and tools; FPGA-based NVMe storage; low power FPGA; SoC FPGA.

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Rambus finalized its acquisition of the silicon IP, secure protocols and provisioning business from Verimatrix, formerly Inside Secure, for $45 million at closing, and up to an additional $20 million, subject to certain revenue targets in 2020.

RISC-V
SiFive unveiled two new product families. The SiFive Apex processor cores target mission-critical processors with Size, Weight, and Power (SWaP) optimization and are generated using the open-source Kami methodology. The SiFive Intelligence processor cores target deep learning markets with vector processing. It uses the RISC-V Vector Extension (RVV) and showed an average performance uplift of 9X vs traditional scalar processing on RISC-V.

Western Digital expanded its open source RISC-V-based SweRV Core family to include a dual-threaded, commercial, embedded RISC-V core, SweRV Core EH2, and the company’s smallest SweRV Core to date, EL2. In addition, the company announced a hardware reference design for OmniXtend, the open “direct to cache over Ethernet” fabric protocol.

Codasip announced a new SweRV Support Package (SSP) to provide  all of the components necessary to design, implement, test, and write software for a SweRV Core EH1-based system-on-chip, including but not limited to verification testbenches and intellectual property, reference scripts for leading EDA flows, models for simulation and emulation, and software development tools.

UltraSoC will offer an open-source implementation of its RISC-V trace encoder via the OpenHW Group. The open-source RISC-V trace solution will be fully compatible with the processor trace standard currently being developed within the RISC-V Foundation’s Processor Trace Working Group. UltraSoC developed the original RISC-V trace encoding algorithm in 2016, donating the specification as open-source shortly afterwards.

FPGA
Aldec launched a new FPGA-based NVMe Data Storage solution to aid in the development of high performance computing (HPC) applications such as High Frequency Trading and machine learning. The solution includes an Aldec TySOM embedded prototyping board and up to eight high-bandwidth, low-latency FMC-NVMe daughter cards, and a reference design (including source files and binaries). The FMC-NVMe card provides four Non-Volatile Memory express (NVMe) interfaces. These are connected to a Microsemi PM8532 PCIe Switch, which provides a connection-to-carrier-card via the PCIe x8 GEN3 interface using a standard FMC connector. The FMC-NVMe daughter card supports board stacking.

Lattice announced Nexus, a new low power FPGA platform. Architectural optimizations for performance at low power include optimized DSP blocks and higher on-chip memory capacity. It is developed on high-volume 28nm FD-SOI process from Samsung and targets a range of applications including AI for IoT, video, hardware security, embedded vision, 5G infrastructure and industrial/automotive automation.

Microchip opened an early access program for its new PolarFire SoC FPGA, which offers a hardened real-time, Linux capable, RISC-V-based microprocessor subsystem on the mid-range PolarFire FPGA family. It includes debug capabilities including instruction trace and passive run-time configurable AXI bus monitors from UltraSoC, 50 breakpoints, FPGA fabric monitors, and built-in two-channel logic analyzer SmartDebug. The PolarFire SoC architecture includes reliability and security features such as single error correction and double error detection (SEC-DED) on all memories, physical memory protection, a DPA resistant crypto core, defense-grade secure boot and 128 Kb of flash boot memory.

Deals
Dialog Semiconductor licensed Flex Logix’s EFLX eFPGA for use in its high-volume ICs, as well as the EFLX Complier. “Adding eFPGA functionality to our products will give our customers the flexibility to keep pace with rapidly changing market needs,” said Davin Lee of Dialog.

Global Unichip Corporation (GUC) selected ANSYS’ RedHawk-SC for full-chip SoC power integrity and reliability signoff. GUC cited the ability to minimize complexity, speed time to market and reduce development costs.

GUC also deployed Cadence’s digital implementation and signoff flow on advanced-node (N16, N12 and N7) designs for AI and high-performance computing (HPC) applications, achieving first-pass silicon success and meeting a GHz performance target for its multi-billion gate designs.

Enflame Technology will use Rambus’ HBM2 PHY and Memory Controller IP for its next-generation AI training chip. Enflame cited the availability of 2Tb/s of bandwidth and high performance of the memory subsystem.

Calterah Semiconductor included Synopsys’ DesignWare ARC EM6 Processor IP in its new-generation advanced CMOS millimeter wave (MMW) radar SoC. Calterah’s new Alps chip series includes four transmitter channels at most, four receiver channels, a highly configurable waveform generator, and an integrated analog-to-digital converter with sampling rates up to 50 MSPS. It also used the ARC MetaWare Development Toolkit for Safety to meet ASIL B requirements.

MediaTek selected Mentor’s ReadyStart edition of the Nucleus RTOS platform for the development of its next-generation modem chipsets, from 2G to 4G, as well as its 5G chipset. MediaTek cited available source code, small footprint, real-time performance, and technical support.

Events
Check out upcoming industry events and conferences: Next year, DesignCon will take place January 28-30 in Santa Clara, CA, with a focus on board and high-speed communications design.



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