Greetings From Mars


Hello Mars. Congratulations to the amazing engineers and scientists at NASA and Jet Propulsion Labs (JPL) for a successful touchdown on the Mars Jezero Crater. In July 2020, NASA launched the Perseverance rover mission, which sought to find signs of habitable conditions, search for biosignatures, and collect samples for future Mars-sample-return missions and human expeditions. Seven months l... » read more

Week In Review: Design, Low Power


Qualcomm finalized its acquisition of data center chip startup Nuvia with a price of $1.4 billion. Nuvia is working on a data center SoC and Arm-based CPU core it claims will lower performance per total cost of ownership by matching high performance with high efficiency and limiting maximum power to that which can be dissipated in an air-cooled environment. Qualcomm said Nuvia’s technology wo... » read more

Enabling Efficient and Flexible FPGA Virtualization for Deep Learning in the Cloud


SOURCE: Shulin Zeng, Guohao Dai, Hanbo Sun, Kai Zhong, Guangjun Ge, Kaiyuan Guo, Yu Wang, Huazhong Yang(Tsinghua University, Beijing, China).  Published on arXiv:2003.12101 [cs.DC])   ABSTRACT: "FPGAs have shown great potential in providing low-latency and energy-efficient solutions for deep neural network (DNN) inference applications. Currently, the majority of FPGA-based DNN accel... » read more

Virtualizing FPGAs For Multiple Cloud Users


Cloud computing has become the new computing paradigm. For cloud computing, virtualization is necessary to enable isolation between users, high flexibility and scalability, high security, and maximized utilization of hardware resources. Since 2017, because of the advantages of programmability, low latency, and high energy efficiency, FPGA has been widely adopted into cloud computing. Amazon ... » read more

Making Sense Of New Edge-Inference Architectures


New edge-inference machine-learning architectures have been arriving at an astounding rate over the last year. Making sense of them all is a challenge. To begin with, not all ML architectures are alike. One of the complicating factors in understanding the different machine-learning architectures is the nomenclature used to describe them. You’ll see terms like “sea-of-MACs,” “systolic... » read more

Blog Review: March 3


Siemens EDA's Ray Salemi considers incrementalism in engineering, the transition from drawing circuits to writing RTL, and the next big leap of using proxy-driven testbenches written in Python. Cadence's Shyam Sharma looks at key changes from LPDDR5 in the LPDDR5X SDRAM standard, which extends clock frequencies to include 937MHz and 1066MHz resulting in max data rates of 7500MT/s and 8533 MT... » read more

Startup Funding: February 2021


In February, several startups emerge from stealth, with one company working on AI inference architectures for the data center and another trying to make lenses thinner by patterning surfaces with tiny structures. Two new Chinese companies are trying to expand the country's semiconductor design ecosystem with GPUs and interface IP. Plus, a maker of AI chips for ADAS draws another massive round t... » read more

Week In Review: Design, Low Power


Cadence completed the acquisition of NUMECA International, a provider of computational fluid dynamics (CFD), mesh generation, multi-physics simulation, and optimization solutions for industries including aerospace, automotive, industrial, and marine. Founded in 1993 as a spin-off of the Vrije Universiteit Brussel (VUB), NUMECA was based in Brussels, Belgium. Terms of the deal were not disclosed... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive/Mobility Toyota Motor Corporation developed a hydrogen fuel cell (FC) system packaged in a compact module. Toyota plans to start selling it in the spring of 2021. The module can be used by other companies developing products powered by fuel cells. Micron is sampling an ASIL D level LPDDR5. The low-power memory is qualified for automotive safety applications. Samsung Foundry ce... » read more

Security In FPGAs And SoCs


Chip security is becoming a bigger problem across different markets, with different emerging standards and more sophisticated attacks. Jason Moore, senior director of engineering at Xilinx, talks with Semiconductor Engineering about current and future threats and what can be done about them. » read more

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