tag: Xilinx

New Approaches To Better Performance And Lower Power
By Ed Sperling - 11 Jul, 2013 - Comments: 0

By Ed Sperling Until 90nm, every feature shrink and rev of Moore’s Law included a side benefit of better power and performance. After that, improvements involved everything from different back-end processes to copper interconnects and transistor structures. But from 20nm onward, the future will rest with a combination of new materials, new architectures and new packaging approaches—and som... » read more

3D-IC Testing With The Mentor Graphics Tessent Platform
By Various Writers - 20 Jun, 2013 - Comments: 0

Three-dimensional stacked integrated circuits (3D-ICs) are composed of multiple stacked die, and are viewed as critical in helping the semiconductor industry keep pace with Moore's Law. Current integration and interconnect methods include wirebond and flip-chip and have been in production for some time. 3D chips connected via interposers are in production at Xilinx, Samsung, IBM, and Sematec... » read more

Experts At The Table: Power Budgeting
By Ed Sperling - 03 Jun, 2013 - Comments: 0

By Ed Sperling Low-Power Engineering sat down with Barry Pangrle, solutions architect for low-power design and verification at Mentor Graphics; Cary Chin, director of technical marketing for low-power solutions at Synopsys; Vic Kulkarni, general manager of the RTL business unit at Apache Design Solutions; Matt Klein, principal engineer for power and broadcast applications at Xilinx; and Paul ... » read more

Using Power Aware IBIS v5.0 Behavioral IO Models To Simulate Simultaneous Switching Noise
By Various Writers - 25 Apr, 2013 - Comments: 0

Typically simultaneous switching noise (SSN) transient simulations require significant CPU and RAM resources. A prominent factor affecting both CPU and RAM resource requirements is the number of MOSFET models included in the post layout extracted IO netlists. By replacing the IO netlists with power aware IBIS v5.0 behavioral models, both the CPU and RAM resource requirements are dramatically re... » read more

The Week In Review: Feb. 25
By Ed Sperling - 25 Feb, 2013 - Comments: 0

By Mark LaPedus Is China set to bail out a U.S. government technology darling? Two Chinese automotive companies, Geely and Dongfeng Motor, are reported to have bid between $200 million and $350 million for a majority stake in Fisker, the maker of plug-in hybrid cars. If that happens Fisker—which has $192 million in U.S. federal government loan guarantees—could be headed to China, according... » read more

Stacked Die From A Networking Angle
By Mark LaPedus - 24 Jan, 2013 - Comments: 1

By Mark LaPedus The first wave of 2.5D chips using silicon interposers are trickling out in the marketplace.FPGA vendor Xilinx was the first chipmaker to ship a 2.5D device, and Altera, Cisco, Huawei and IBM recently have talked about their respective 2.5D chip developments. Generally, Altera and Xilinx have taken a somewhat identical and straightforward approach. The two companies are sepa... » read more

Foundry Landscape Changes In 3D
By Mark LaPedus - 13 Dec, 2012 - Comments: 0

By Mark LaPedus Over the last year, leading-edge silicon foundries announced their new and respective strategies in the emerging 2.5D/3D chip arena. The ink is barely dry and now the foundry landscape is changing. One new vendor, Tezzaron Semiconductor, is entering the market. The 3D DRAM supplier plans to provide select 2.5D/3D foundry services within its recently acquired fab in Austin, T... » read more

Straight Talk On 3D TSVs
By Ed Sperling - 13 Dec, 2012 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss 3D device challenges and applications with John Lau, a fellow at the Industrial Technology Research Institute (ITRI), a research organization in Taiwan. SMD: What is ITRI doing in 3D TSVs? Lau: At ITRI we have developed the world’s first Applied Materials’ 300mm (3D TSV) integration line. The line was comple... » read more

Chip Architect Challenges
By Ed Sperling - 06 Dec, 2012 - Comments: 0

By Ann Steffora Mutschler Product lifecycles can be shorter than the design cycle and even the process development cycle, particularly in the consumer handheld device market. It’s up to the chip architect to decide how the functions should be implemented. The good news is there are a number of options available, ranging from mapping the design to 2.5D technology, moving to finFET tr... » read more

Prototyping Now A ‘Must Have’
By Ed Sperling - 29 Nov, 2012 - Comments: 0

By Ann Steffora Mutschler No longer a ‘nice to have,’ FPGA-based prototyping is now indispensible for SoC and ASIC development. Semiconductor companies are investing in the infrastructure, the EDA tool chain, the human resources and everything needed to set up an entire department to focus on prototyping, emulation and validation. “We are seeing these customers invest in significant a... » read more

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