tag: Xilinx

Node Skipping Reaches New Heights
By Ed Sperling - 15 Nov, 2012 - Comments: 0

By Mark LaPedus For years, silicon foundries have rolled out their respective leading-edge processes roughly on a two-year cadence. The long-standing goal has been to keep foundry customers on a competitive price, power and performance curve. But as leading-edge chipmakers move from the 28nm node and beyond, the predictable process progression is changing. And the phenomenon of “node skip... » read more

Experts At The Table: FPGA Prototyping Issues
By Ed Sperling - 27 Sep, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss challenges in the FPGA prototyping world with Troy Scott, product marketing manager at Synopsys; Tom Feist, senior director of marketing at Xilinx; Shakeel Jeeawoody, vice president of marketing at Blue Pearl Software; and Ralph Zak, business development director at EVE. What follows are excerpts of that discussion. SLD: As we go forwar... » read more

SPOTLIGHT ON FD-SOI, FINFETS AT IEEE SOI CONFERENCE
;1-4 OCT, NAPA
By Various Writers - 25 Sep, 2012 - Comments: 0

The 38th annual SOI Conference is coming right up. Sponsored by IEEE Electron Devices Society, this is the only dedicated SOI conference covering the full technology chain from materials to devices, circuits and system applications. Chaired this year by Gosia Jurczak (manager of the Memories Program at imec), this excellent conference is well worth attending. It’s where the giants of the ... » read more

Experts At The Table: FPGA Prototyping Issues
By Ed Sperling - 07 Sep, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss challenges in the FPGA prototyping world with Troy Scott, product marketing manager at Synopsys; Tom Feist, senior director of marketing at Xilinx; Shakeel Jeeawoody, vice president of marketing at Blue Pearl Software; and Ralph Zak, business development director at EVE. What follows are excerpts of that discussion. SLD: Are FPGAs star... » read more

Experts At The Table: FPGA Prototyping Issues
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss challenges in the FPGA prototyping world with Troy Scott, product marketing manager at Synopsys; Tom Feist, senior director of marketing at Xilinx; Shakeel Jeeawoody, vice president of marketing at Blue Pearl Software; and Ralph Zak, business development director at EVE. What follows are excerpts of that discussion. SLD: Where are the ... » read more

Firms Rethink Fabless-Foundry Model
By Ed Sperling - 31 Jul, 2012 - Comments: 0

By Mark LaPedus As chipmakers move toward 20nm designs, finFETs and 3D stacked devices, the industry is beginning to re-think the fabless-foundry model. Leading-edge foundries are finally getting serious about the “virtual IDM” model, in which vendors will act more like integrated device manufacturers (IDMs), as opposed to being mere production partners. In this model, the found... » read more

Stacking The Deck
By Matt Elmore - 12 Jul, 2012 - Comments: 0

By Matt Elmore Can we finally say that 3D-IC design has emerged from the realm of theory and research to actual commercial implementation? Xilinx recently announced initial shipments of its Virtex-7 H580T FPGA, described as “The world’s first 3D heterogeneous all programmable product.” The benefits of 3D implementation are many, as are its challenges. One of the hottest 3D-IC topics t... » read more

How Firm Is Firmware?
By Frank Schirrmeister - 26 Jun, 2012 - Comments: 0

By Frank Schirrmeister When blogging recently about Xilinx’s presentation at the Cadence DAC 2012 EDA360 theater, which was given by Dave Beal, I ran across the diagram he had used to outline the “development stack” from hardware to software. Dave had described a virtual prototype to the audience as a functional model that recreates the WHAT rather than the HOW, duplicating the result ... » read more

Options And Hurdles Come Into Focus For 3D Stacking
By Ed Sperling - 29 May, 2012 - Comments: 0

By Mark LaPedus The initial round of stacked 2.5D and 3D chips based on through-silicon vias (TSVs) has emerged in the market. There are other 2.5D/3D chips in the pipeline, but it’s taking longer than expected to bring these devices into production. There are a range of design, manufacturing, supply chain and cost challenges associated with 2.5D/3D designs. The enormous risk to bring ... » read more

Getting Ready For Stacked Die
By Ed Sperling - 05 Apr, 2012 - Comments: 0

By Ed Sperling The move toward stacking of die has always been a series of disconnected pieces and vague promises for the future, but in the past few months the scenario has changed radically—and so has the commentary. All three of the Big Three EDA vendors now have at least some of the pieces in place for 2.5D stacking and are working on a full 3D flow. Two of the biggest FPGA vendors, A... » read more

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