Dealing With Resistance In Chips

By Mark LaPedus - 21 Jun, 2018 - Comments: 2

Chipmakers continue to scale the transistor at advanced nodes, but they are struggling to maintain the same pace with the other two critical parts of the device—the contacts and interconnects. That’s beginning to change, however. In fact, at 10nm/7nm, chipmakers are introducing new topologies and materials such as cobalt, which promises to boost the performance and reduce unwanted resist... » read more

Advanced 3D Design Technology Co-Optimization For Manufacturability

By Yu De Chen - 30 Apr, 2018 - Comments: 0

By Yu De Chen, Jacky Huang, Dalong Zhao, Jiangjiang (Jimmy) Gu, and Joseph Ervin Yield and cost have always been critical factors for both manufacturers and designers of semiconductor products. It is a continuous challenge to meet targets of both yield and cost, due to new device structures and the increasing complexity of process innovations introduced to achieve improved product performanc... » read more

The Next 5 Years Of Chip Technology

By Ed Sperling - 14 Mar, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss the future of scaling, the impact of variation, and the introduction of new materials and technologies, with Rick Gottscho, CTO of Lam Research; Mark Dougherty, vice president of advanced module engineering at GlobalFoundries; David Shortt, technical fellow at KLA-Tencor; Gary Zhang, vice president of computational litho products at ASML; and Shay... » read more

7/5nm Timing Closure Intensifies

By Ann Mutschler - 25 Jan, 2018 - Comments: 1

Timing closure issues are increasing in magnitude at 7/5nm, and ones that were often considered minor in the past no longer can be ignored. Timing closure is an essential part of any chip design. The process ensures that all combinatorial paths through a design meet the necessary timing so that it can run reliably at a specified clock rate. Timing closure hasn't changed significantly over th... » read more

Pattern-Based Analytics To Estimate And Track Yield Risk Of Designs Down To 7nm

By Cadence - 24 Jan, 2018 - Comments: 0

Topological pattern-based methods for analyzing IC physical design complexity and scoring resulting patterns to identify risky patterns have emerged as powerful tools for identifying important trends and comparing different designs. In this paper, previous work is extended to include analysis of layouts designed for the 7nm technology generation. A comparison of pattern complexity trends with r... » read more

E-beam Inspection Makes Inroads

By Mark LaPedus - 18 Jan, 2018 - Comments: 4

E-beam inspection is gaining traction in critical areas in fab production as it is becoming more difficult to find tiny defects with traditional methods at advanced nodes. Applied Materials, ASML/HMI and others are developing new e-beam inspection tools and/or techniques to solve some of the more difficult defect issues in the fab. [gettech id="31057" t_name="E-beam"] inspection is one of tw... » read more

Methodology For Analyzing And Quantifying Design Style Changes And Complexity Using Topological Patterns

By Cadence - 10 Jan, 2018 - Comments: 0

In order to maximize yield, IC design companies spend a lot of effort to analyze what types of design styles are needed and used in their layouts (standard cells, macros, routing layers, and so forth). This paper introduces a novel methodology for full chip high performance topological pattern analysis and the applications of this methodology towards analyzing design styles in order to quanti... » read more

How To Sleep Easier If You Test Auto ICs For A Living

By Andrew Macleod - 07 Dec, 2017 - Comments: 0

Last month, I looked at the product definition process of automotive ICs, using the $7 billion microcontroller market as an illustration of design exploration to optimize performance, features, die size and product cost. Now I’d like to look at the back end of the process — the final IC testing that’s still critical no matter how sound the upfront work in defining a featuring set and aptl... » read more

Improving Yield, Reliability With Data

By Ann Mutschler - 11 Oct, 2017 - Comments: 0

Big data techniques for sorting through massive amounts of data to identify aberrations are beginning to find a home in semiconductor manufacturing, fueled by new requirements in safety-critical markets such as automotive as well as the rising price of packaged chips in smartphones. Outlier detection—the process of finding data points outside the normal distribution—isn't a new idea. It ... » read more

Filtering Out Fab Problems

By Mark LaPedus - 20 Jul, 2017 - Comments: 1

Bertrand Loy, president and CEO of Entegris, sat down to discuss the semiconductor industry, process challenges and filter technology with Semiconductor Engineering. What follows are excerpts of that conversation. SE: What is the outlook for the IC industry? Loy: A lot of positive things are happening. Eighty percent of what we do are consumables, which would be chemistries and filters. ... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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