tag: yield

LP Test Strategies
By Luke Lang - 13 Sep, 2012 - Comments: 0

By Luke Lang Power during test is one area that is often overlooked. In the worst (but easiest to diagnose) case, excessive test power can lead to a smoking chip on the tester. (You don’t need an engineering education to see the problem.) In a better (but more difficult to diagnose) case, excessive test power will cause reduced yield. Let’s look at what causes excessive test power and how ... » read more

Boosting Yield With Layout Awareness
By Ed Sperling - 26 Apr, 2012 - Comments: 0

By Ann Steffora Mutschler Yield. Just the word can make many engineers cringe and hide in their cubicles—especially with manufacturing problems and excessive power during test increasing causing failures. But the combination of physical data with diagnostics engines may be the light at the end of the tunnel, allowing for easier pinpointing of defects. There are many reasons why a chip fai... » read more

Experts At The Table: Improving Yield
By Ed Sperling - 07 Nov, 2011 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down to discuss yield issues with Sesh Ramaswami, senior director of strategy at Applied Materials; Luigi Capodieci, R&D fellow at GlobalFoundries; Kimon Michaels, vice president and DFM director at PDF Solutions; Mike Smayling, senior vice president at Tela Innovations; and Mark Mason, director of data integration at Texas Instr... » read more

Experts At The Table: Improving Yield
By Ed Sperling - 27 Oct, 2011 - Comments: 0

y Ed Sperling Semiconductor Manufacturing & Design sat down to discuss yield issues with Sesh Ramaswami, senior director of strategy at Applied Materials; Luigi Capodieci, R&D fellow at GlobalFoundries; Kimon Michaels, vice president and DFM director at PDF Solutions; Mike Smayling, senior vice president at Tela Innovations; and Mark Mason, director of data integration at Texas Instrum... » read more

Different Ways To Boost Yield
By Ed Sperling - 30 Jun, 2011 - Comments: 0

By Ann Steffora Mutschler In the race to get products to market with shortening product cycles, steepening the ramp to yield is critical. The introductory phase of a product is the point at which margins are highest and market share can be most easily gained. This is no surprise to chipmakers. What is surprising is just how much more difficult it has become to achieve acceptable yield quick... » read more

IC Yield Issues
By Ed Sperling - 27 May, 2011 - Comments: 0

What makes one semiconductor design yield better than another. And what issues are we likely to face going forward. Semiconductor Manufacturing & Design questions Amiad Conley from Applied Materials; Cyrus Tabery from GlobalFoundries; Brady Benware from Mentor Graphics, and Ankush Oberai from Magma. [youtube vid=1YjY436YmNQ] » read more

Experts At The Table: Yield Issues
By Ed Sperling - 22 Apr, 2011 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down to discuss yield with Amiad Conley, technology marketing manager for yield and process control at Applied Materials; Cyrus Tabery, senior member of the GlobalFoundries technical staff for lithography development and DFM; Brady Benware, engineering manager for diagnosis and yield at Mentor Graphics, and Ankush Oberai, general man... » read more

Experts At The Table: Yield Issues
By Ed Sperling - 10 Apr, 2011 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down to discuss yield with Amiad Conley, technology marketing manager for yield and process control at Applied Materials; Cyrus Tabery, senior member of the GlobalFoundries technical staff for lithography development and DFM; Brady Benware, engineering manager for diagnosis and yield at Mentor Graphics, and Ankush Oberai, general man... » read more

Experts At The Table: Yield Issues
By Ed Sperling - 27 Mar, 2011 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down to discuss yield with Amiad Conley, technology marketing manager for yield and process control at Applied Materials; Cyrus Tabery, senior member of the GlobalFoundries technical staff for lithography development and DFM; Brady Benware, engineering manager for diagnosis and yield at Mentor Graphics, and Ankush Oberai, general man... » read more

Rethinking Test
By Ann Mutschler - 11 Feb, 2010 - Comments: 0

By Ann Steffora Mutschler The responsibility of semiconductor test has long sat solely with the test engineer as the chip designer focused on the functionality of the device. However, particularly in low-power designs, when the device is being tested, much higher power levels are applied than normal functional operation – sometimes causing the device to fail. This ‘false failure’ c... » read more

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