Improving Semiconductor Yield Using Large Area Analysis

By Jacky Huang - 19 Dec, 2023 - Comments: 0

Design rule checking (DRC) is a technique used during chip design to ensure that a device can successfully be manufactured at high yield. Design rules are established based on the limits and variability of equipment and process technologies in use. DRC checking ensures that a design meets manufacturing requirements and will not result in a chip failure or DRC “violation.” Common DRC rules i... » read more

Total Overlay With Multiple RDLs

By Ed Sperling - 13 Nov, 2023 - Comments: 0

As Advanced IC Substrates (AICS) add more RDL layers, requiring additional via connections between the RDL layers, the potential for cumulative overlay shift increases. This overlay shift can lead to longer RDL traces, which increases interconnect resistance, resulting in lower yield. Keith Best, director of product marketing, for lithography at Onto Innovation, talks about total overlay — th... » read more

Rebalancing Test And Yield In IC Manufacturing

By Gregory Haley - 07 Nov, 2023 - Comments: 0

Balancing yield and test is essential to semiconductor manufacturing, but it's becoming harder to determine how much weight to give one versus the other as chips become more specialized for different applications. Yield focuses on maximizing the number of functional chips from a production batch, while test aims to ensure that each chip meets rigorous quality and performance standards. And w... » read more

Installing Yield Software Early In A Ramp Up

By Dieter Rathei - 10 Oct, 2023 - Comments: 0

In 1999, the White Oak Semiconductor Fab in Richmond, VA, was awarded the prestigious “Top Fab of the Year” (yes, that actually existed – proof attached!) by the leading semiconductor magazine of the time. Back then, I was a young engineer on the ramp up team and I recall that the reason we were chosen for the award was the incredibly short time in which we were able to ramp up production... » read more

Customizing IC Test To Improve Yield And Reliability

By Ed Sperling - 12 Sep, 2023 - Comments: 0

Testing the performance and power of semiconductors as they come off the production line is beginning to shift left in the fab, reversing a long-standing trend of assessing chips just prior to shipping. While this may sound straightforward, it's a difficult challenge which, if successful, will have broad implications for the entire design-through-manufacturing flow. Manufacturers typically g... » read more

Test Strategies In The Era Of Heterogeneous Integration

By Fisher Zhang - 12 Sep, 2023 - Comments: 0

Moore’s Law, the observation that the number of transistors on an integrated circuit doubles approximately every two years, is critical to advances in computing technology. For decades, fabs have managed to achieve exponential growth in digital capability and transistor density by making transistors smaller and smaller, but we’ve hit the physical limits of these processes. Today, new proces... » read more

Addressing Copper Clad Laminate Processing Distortion Using Overlay Corrections

By Keith Best - 11 Jul, 2023 - Comments: 0

All great voyages must come to an end. Such is the case with our series on the challenges facing the manufacturing of advanced IC substrates (AICS), the glue holding the heterogeneous integration ship together. In our first blog, we examined how cumulative overlay drift from individual redistribution layers could significantly increase overall trace length, resulting in higher interconnect res... » read more

Smart Manufacturing Makes Gains In Chip Industry

By Anne Meixner - 15 Jun, 2023 - Comments: 0

Lights out manufacturing is gaining steam across the semiconductor industry, accelerating productivity, improving quality, and reducing costs and environment impact. These benefits are the result of years of strategic investments in technologies like machine-to-machine communication, data analytics, and robotics to achieve higher levels of autonomy. Semiconductor factories have long depen... » read more

Multivariate Analysis For Full Process Visibility

By Krista Tropper - 06 Jun, 2023 - Comments: 0

In semiconductor manufacturing, especially in electrical test data, but also in other parameters, there are often sets of parameters that are very highly correlated. Even a change in the correlation of those parameters may indicate a problem. For that reason, multivariate monitoring, or multivariate statistics, is applied to these parameters. Multivariate analysis, also known as multivariate... » read more

Challenges Grow For Creating Smaller Bumps For Flip Chips

By Anne Meixner - 18 May, 2023 - Comments: 0

New bump structures are being developed to enable higher interconnect densities in flip-chip packaging, but they are complex, expensive, and increasingly difficult to manufacture. For products with high pin counts, flip-chip [1] packages have long been a popular choice because they utilize the whole die area for interconnect. The technology has been in use since the 1970s, starting with IBM�... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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