Silicon Lifecycle Management Advances With Unified Analytics


In a typical day in the life of a product engineer, they have gone through the requisite wafer sort testing in manufacturing with the next step to assemble the resultant good die into their respective packages. While performing a series of parametric tests during final test, yield issues are encountered and the process of finding the source of the issues begins. Luckily, with access to a good d... » read more

What Is Achievable With A Yield Management System?


Semiconductor manufacturers are under constant pressure to increase yields and cut costs. Yield Management Systems (YMS) are designed specifically to meet the needs of semiconductor manufacturers, enabling them to investigate yield excursions, streamline the manufacturing processes, optimize the supply chain, analyze tools and eliminate workplace inefficiencies. In terms of data challenges... » read more

What Data Center Chipmakers Can Learn From Automotive


Automotive OEMs are demanding their semiconductor suppliers achieve a nearly unmeasurable target of 10 defective parts per billion (DPPB). Whether this is realistic remains to be seen, but systems companies are looking to emulate that level of quality for their data center SoCs. Building to that quality level is more expensive up front, although ultimately it can save costs versus having to ... » read more

Challenges Grow For CD-SEMs At 5nm And Beyond


CD-SEM, the workhorse metrology tool used by fabs for process control, is facing big challenges at 5nm and below. Traditionally, CD-SEM imaging has relied on a limited number of image frames for averaging, which is necessary both to maintain throughput speeds and to minimize sample damage from the electron beam itself. As dimensions get smaller, these limitations result in higher levels of n... » read more

Using Machine Learning To Increase Yield And Lower Packaging Costs


Packaging is becoming more and more challenging and costly. Whether the reason is substrate shortages or the increased complexity of packages themselves, outsourced semiconductor assembly and test (OSAT) houses have to spend more money, more time and more resources on assembly and testing. As such, one of the more important challenges facing OSATs today is managing die that pass testing at the ... » read more

Leveraging Chip Data To Improve Productivity


The semiconductor ecosystem is scrambling to use data more effectively in order to increase the productivity of design teams, improve yield in the fab, and ultimately increase reliability of systems in the field. Data collection, analysis, and utilization is at the center of all these efforts and more. Data can be collected at every point in the design-through-manufacturing flow and into the f... » read more

Silent Data Corruption


Defects can creep into chip manufacturing from anywhere, but the problem is getting worse at advanced nodes and in advanced packages where reduced pin access can make testing much more difficult. Ira Leventhal, vice president of U.S. Applied Research and Technology at Advantest America, talks about what’s causing these so-called silent data errors, how to find them, and why it now requires ma... » read more

Next Steps For Improving Yield


Chipmakers are ramping new tools and methodologies to achieve sufficient yield faster, despite smaller device dimensions, a growing number of systematic defects, immense data volumes, and massive competitive pressure. Whether a 3nm process is ramping, or a 28nm process is being tuned, the focus is on reducing defectivity. The challenge is to rapidly identify indicators that can improve yield... » read more

How To Improve Yield Ramp For New Designs And Technology Nodes


The complicated silicon defect types and defect distribution of new IC manufacturing technologies can result in very low yield for new designs and technology nodes. During technology qualification using test chips, scan chain failures account for most of the chip failures. Diagnosing those scan chain defects is a powerful way to uncover new and systematic defects. The chip maker’s goal is ... » read more

Test Connections Clean Up With Real-Time Maintenance


Test facilities are beginning to implement real-time maintenance, rather than scheduled maintenance, to reduce manufacturing costs and boost product yield. Adaptive cleaning of probe needles and test sockets can extend equipment lifetimes and reduce yield excursions. The same is true for load board repair, which is moving toward predictive maintenance. But this change is much more complicate... » read more

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