tag: Yonsei University

Chip Industry Technical Paper Roundup: August 20
By Linda Christensen - 20 Aug, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=252 /] More ReadingTechnical Paper Library home » read more

Potential Of 2D Semi-Metallic PtSe2 As Source/Drain Contacts For 2D Material FETs
By Technical Paper Link - 13 Aug, 2024 - Comments: 0

A technical paper titled “Improvement of Contact Resistance and 3D Integration of 2D Material Field-Effect Transistors Using Semi-Metallic PtSe2 Contacts” was published by researchers at Yonsei University, Korea Advanced Institute of Science and Technology (KAIST), Lincoln University College, Korea Institute of Science and Technology (KIST), and Ewha Womans University. Abstract: "In this ... » read more

Research Bits: Jan. 23
By Jesse Allen - 23 Jan, 2024 - Comments: 0

Memristor-based Bayesian neural network Researchers from CEA-Leti, CEA-List, and CNRS built a complete memristor-based Bayesian neural network implementation for classifying types of arrhythmia recordings with precise aleatoric and epistemic uncertainty. While Bayesian neural networks are useful for at sensory processing applications based on a small amount of noisy input data because they ... » read more

Research Bits: Dec. 18
By Jesse Allen - 18 Dec, 2023 - Comments: 0

Stacking 2D layers for AI processing Researchers from Washington University in St. Louis, MIT, Yonsei University, Inha University, Georgia Institute of Technology, and the University of Notre Dame demonstrated monolithic 3D integration of layered 2D material, creating a novel AI processing hardware that integrates sensing, signal processing, and AI computing functions into a single chip. Th... » read more

Chip Industry’s Technical Paper Roundup: July 24
By Liz Allan - 24 Jul, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=119 /] More Reading Technical Paper Library home » read more

A 3D MEMS Coaxial Socket Overcomes Challenges In Semiconductor Package Chip Testing
By Technical Paper Link - 20 Jul, 2023 - Comments: 0

A technical paper titled "Fabrication and Characterization of Three-Dimensional Microelectromechanical System Coaxial Socket Device for Semiconductor Package Testing" was published by researchers at Yonsei University and Protec MEMS Technology. Abstract: "With the continuous reduction in size and increase in density of semiconductor devices, there is a growing demand for contact solutions tha... » read more

Research Bits: March 6
By Jesse Allen - 06 Mar, 2023 - Comments: 0

2D TMDs on silicon Engineers at MIT, University of Texas at Dallas, Institute for Basic Science, Sungkyunkwan University, Washington University in St. Louis, University of California at Riverside, ISAC Research, and Yonsei University found a way to grow 2D materials on industry-standard silicon wafers while preserving their crystalline form. Using a new “nonepitaxial, single-crystalline g... » read more

Technical Paper Round-Up: July 26
By Linda Christensen - 26 Jul, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=41 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit f... » read more

Film Failure in Multilayer Systems for Semiconductor Devices
By Technical Paper Link - 18 Jul, 2022 - Comments: 0

Researchers at MIT, Yonsei University (Seoul, Korea) just published this technical paper titled "Interfacial Delamination at Multilayer Thin Films in Semiconductor Devices." According to the abstract "In this work, the effect of thermomechanical stress on the failure of multilayered thin films on Si substrates was studied using analytical calculations and various thermomechanical tests." ... » read more

Research Bits: June 21
By Jesse Allen - 21 Jun, 2022 - Comments: 0

Side-channel protection for edge AI Researchers from the Massachusetts Institute of Technology built a chip that can defend against power side-channel attacks targeting machine learning computations in smartwatches, smartphones, and tablets. Side-channel attacks involve observing a facet of the device's operation, in this case power, to deduce secrets. “The goal of this project is to buil... » read more

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