Gleaning useful information well before all the details of an assembly are known.
As the industry marches forward in a 3D-IC centric design approach (figure 1), we are facing a new problem. Sometimes referred to as “electro-thermal” or “electro-thermo-mechanical,” it really is the confluence of multiple forms of physics exerting impacts on both the physical manufacture and structure of these multi-die designs and their electrical behavior.
Fig. 1: Illustration of a 3D-IC assembly.
Put simply, we know that changes in temperatures impact electrical behavior of both wires and transistor-level devices. Similarly, mechanical stresses can also impact the circuitry behavior. When we think about the consequences of these combining issues, the implications are quite huge with respect to the long-held desire of a design environment where chiplets in the form of hard IP can be dropped in to a 3D heterogeneous design assembly and work out of the box. In fact, even the concept of known-good-die has to be rethought.
Consider the traditional die sorting approach. Dies are placed on a test bench and measurements are made to validate that signals arrive at various locations with the right voltages and at the right time. Now consider the case when such dies are placed into an assembly containing several other dies from multiple processes and potentially even multiple fabs. Each die is working under different power conditions while also surrounded in all physical dimensions by other chiplets, bumps, package materials, TSVs and copper pillars, even down to BGAs. The changes in power will impact the temperatures of the chiplet within the context of the assembly. Similarly, all the other physical structures will exert mechanical stresses onto the active chiplets. As these chiplets are no longer in the same physical environment as when they were on the test bench, we can no longer assume that they will still behave electrically as they did at test!
As if that is not bad enough, there is also a cyclical nature to the problem. In particular, it is the act of powering devices by pushing electrons through copper wires that produces heat. But, as indicated, heat changes the circuit behavior. This in turn implies that the original power estimation itself cannot be fully trusted! Power and thermal co-analysis becomes critical to find where, or if, there is a stabilization point.
Of course, power and thermal analysis capabilities and, to a lesser extent, the ability to calculate mechanical stresses at the nanometer level exist today. In theory, a designer can perform these at the assembly design level to identify problematic areas. But there are still challenges: First is the difficulty of converting these physical phenomena into the corresponding electrical impacts. Second is the business impact of designing a very complex assembly with multiple heterogeneous chiplets in three dimensions only to find a problem at sign-off.
So what does a practical solution look like? First, we have to consider that, given the ability to place chiplets in three dimensions and interconnect between them in multiple ways, there can be a near limitless number of ways to combine them to form the intended circuitry. But how to know which combination is optimal? Addressing this requires the ability to generate multiple possible assembly configurations while performing analysis across them all.
This is where a shift-left strategy comes in. Analysis of the multiphysics effects of 3D-ICs (thermal, mechanical, etc.) in the chiplets and assembly needs to be done not just at the final design stage, but at the very beginning of design planning. Figure 2 illustrates the turn-around-time (TAT) benefits of a shift-left strategy.
Fig. 2: Don’t wait until sign-off to find critical issues in the 3D assembly. Shift left design solutions improve productivity and design quality while reducing time to market.
Of course, the best possible accuracy only comes when all details of the assembly, including the chiplet placements, the power supply infrastructure, the chiplet circuitry and even the intended working conditions are known. But designers can glean useful information well before all the details are known. At the earliest assembly design stages, the dies can be treated as simple uniform structures and simple static coefficients can be used for early power estimations. Hot-spot analysis can be performed to identify stacking configurations that have obvious thermal and/or mechanical issues. Performing such analysis across multiple possible configurations in parallel allows the designer to make intelligent decisions on configurations that are more likely to lead to success.
As the chiplets begin to mature, perhaps front end of line or back end of line only, more analysis can be performed to achieve better accuracy, leading to further weeding of assembly types, or manual fine tuning of the design to address specific problem areas.
As the individual chiplet power is better understood, the detailed power models can be used and can even be fed into a greater assembly level power analysis. This will help to more accurately capture the thermal impacts. Ultimately, as the details converge, both the thermal and mechanical impacts can be converted to electrical impacts. By pushing the impacts to the specific active chiplet circuit levels, they can be captured in the form of spice level netlists for simulation. Users can use this to drive timing analysis, EMIR, power analysis and signal analysis. Assuming the impacts have been captured across the full assembly, each chiplet, or specific subcircuits can be analyzed individually.
Of course, analyzing the full assembly requires a bit more. Today the industry is still struggling with how to represent a full assembly circuit netlist. Some will treat chiplets completely as black boxes. Others will try to verify proper inter-chiplet connectivity with separate LVS decks and runs for each specific interface. Proper circuit level verification will require more. While it is physically possible to extract a full post-assembly netlist, it is very difficult to support at the foundry or OSAT level because in most cases, they do not have sufficient knowledge of what actually resides in the assembly. Industry available formats, such as the 3Dblox standard, can help but still require an environment from which to generate them.
Design planning tools are also helpful in this situation. With the proper knowledge of each chiplet’s placement and all the pin-to-pin connections, a top-level netlist can be extracted and compared against a generated source netlist. With inclusion of the individual chiplet circuitry, a more complete description can be gained. In fact, in some cases, such as chiplet-on-package redistribution layer (RDL) interfaces or die-to-die hybrid-bonding scenarios where the wires of the interfacing components are very close physically, parasitic couplings between chiplets can also be extracted. Combining all of this information together with the previously described thermal and mechanical impacts on the circuitry creates the final sign-off level of accuracy for the full assembly. Figure 3 illustrates the components of a more unified 3D-IC flow with extended verification.
Fig. 3: Design automation tools can provide a cockpit to unify 3D-IC assembly, floorplanning, routing, and simulation with verification throughout the flow.
Of course, as these 3D-IC designs quickly grow in size in terms of number of transistors compared to traditional full-reticle, performing these simulations across many different corners poses yet another challenge. The semiconductor ecosystem, including the Calibre physical verification solutions, will tackle that challenge too, enabling continued progress for 3D-IC designs.
John Ferguson, “Reduce 3DIC design complexity with early package assembly verification,” Siemens EDA technical paper, December 2023
N. Hossam and J. Ferguson, “Fast, Accurate Assembly-Level Physical Verification of 3DIC Packages,” 2023 IEEE International 3D Systems Integration Conference (3DIC), Cork, Ireland, 2023.
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