The Great Imbalance

The number of options for chipmakers is growing while the number of chipmakers is shrinking. So what does this mean for the semiconductor industry? Short answer: No one is quite sure yet. But a lot more people are beginning to ask that question these days, including investors and analysts.

There are a number of factors at play here. To begin with, there are more nodes to choose from than at anytime in the past, and notably more than one that could work well for any specific application. A 28nm process may suffice for the next several years if price is a consideration, and it actually may be a market advantage if competitors move to finFETs and can’t sell enough volume to warrant the investment. Unlike in the past, when companies could count on everyone moving to the next node every couple years, including their competitors, the market dynamics have shifted considerably.

The addition of FD-SOI at 28nm and now 22nm, along with increased availability of silicon germanium, clouds the issue even further. So now, instead of just choosing between process nodes, chipmakers have to weigh process nodes using bulk CMOS versus nodes using FD-SOI—or other more specialized materials.

There are more choices at each node using the same materials, too. Those may be easier to figure out when focusing on one application in a known market with well-understood use cases, but that’s not so obvious in developing markets such as the IoT. Moreover, it’s much tougher to figure out from one foundry to another. After 40nm, processes began diverging significantly from one foundry to the next. The specs are easy enough to read for sophisticated chipmakers, but the availability of optimized, off-the-shelf IP and EDA tools is much harder to digest.

Add to that more architectural choices—2.5D, 3D, fan-outs, on-chip memory, off-chip memory—along with continued uncertainty over lithography, and the number of variables becomes almost mind-boggling.

Major chipmakers can make almost anything work. Much has been made about the leakage current at 20nm, which prompted foundries to invest billions of dollars in finFETs and begin work on next-generation 3D structures such as gate-all-around FETs and nanowire FETs. Yet some of the highest volume chips in production today, including those used in the leading smartphones, still use 20nm planar technology.

So why all of these choices? The simple answer is that foundries are revving up for new markets such as the IoT and all of its permutations—medical, automotive, home, industrial—where more options need to be explored to see what sticks. Just as there were hundreds of wearable electronics devices on display at the Consumer Electronics Show this year, there are dozens of options being prepared to manufacture them and bring them to market. The most conservative estimates for the IoT are the tens of billions of devices, while the more optimistic are in the hundreds of billions range.

No one expects every idea or process or material to survive. Despite predictions about billions of things talking to other things, the number of companies making those things will consolidate and the number of options for making them will dwindle. But no one wants to be caught without enough options to offer to chipmakers and their customers while that market gets sorted out. Until then, the semiconductor market will likely get even more confusing before the winners are selected. And after that, the industry can take everything it learned and optimize it for PPA and manufacturability, which is what has propelled it forward for the past half century.