The Reliability Of Analog Integrated Circuits And Their Simulation-Aided Verification

Different challenges have to be overcome when designing integrated circuits. Besides schematic and layout design work, verification in view of the non-ideal behavior of circuits and semiconductor technologies in particular is also relevant.

• The designed circuits have to work at specific operating voltages and within ambient temperature ranges and be robust in terms of process fluctuations and microscopic variations.
• The interaction of the integrated circuit and design and connection technology, referred to as chip-package interaction (CPI), causes mechanical tensions that affect the behavior of integrated transistors in different ways, depending on their position in the overall system.
• Integrated transistors age due to effects such as hot carrier injection (HCI) and bias temperature instability (BTI). This means their electrical behavior changes over time and depending on load and temperature.

The exact relevance of these effects depends heavily on the product itself, the intended application scenario with its ambient conditions, and any special requirements, from the design style with the corresponding approach to these challenges to the semiconductor and packaging technologies used. In general, extremely scaled technologies appear to derive their benefits in the area of performance, with disadvantages as seen in the challenges named above.

Various questions become of interest during verification in analog design. The first thing to be clarified is how relevant and critical the effects indicated above are for the actual project. Next, their effects have to be investigated and countermeasures taken as needed.

Different analytical approaches and the corresponding tools make it possible to examine different influencing factors and their effects on the behavior of components and circuits virtually during the design phase. However, this requires appropriate models, and formulating and parameterizing them entails an immense amount of work.

The effects of HCI and BTI in a specific semiconductor technology are examined during technology qualification. In corresponding experiments on individual transistors, a constant overstress is applied in order to be able to observe measurable degradation within a reasonable period of time. This kind of measurement often takes 10,000 seconds, or just under three hours. In the result, changes to selected parameters, such as the threshold voltage VTH, saturation current IDSAT, or maximum transconductance GMAX, can be described interdependent with load, temperature, and time in what is referred to as wafer level reliability models.

However, when operating an integrated circuit, a distinct electrical load is applied to each transistor, and it therefore degrades distinctively. This leads to two major questions for an IC designer.

1. To what extent do the individual transistors in a circuit degrade due to “normal” operation?
2. How do these changes in total affect the behavior of the overall circuit?

These questions can be answered based on simulations. It must be taken into consideration that transistors in operation are not generally subjected to a constant overstress, but rather to a time-varying lower load, and that the circuits they comprise still have to work for years. Conveniently, WLR models are usually designed to enable an extrapolation to lower voltages and currents, that is, normal operating conditions instead of overstress and service lives in the range of years, as well as to support time-dependent signal curves.

Methods that use the load on a transistor as the input variable and calculate the expected degradation with the help of WLR models are suitable for answering question one. This kind of approach is available for individual transistors and is being developed for complete circuits, as all of the transistors in a circuit are also taken into consideration, including feedback to the designer in their familiar work environment. As a result, information on expected degradation is given to the designer and, in combination with their expertise, an assessment of the severity of these changes can be made.

Aging simulations have been a part of different circuit simulators for the verification of analog circuits for some time now. They complement standard SPICE simulations to provide answers to question two. With the help of aging models, they transform the expected degradation of a transistor into a simulatable form. The parameters of the underlying compact transistor models are frequently customized. Alternatively, equivalent circuits can emulate transistor degradation. This results in a virtual description of the circuit after a certain operating period in a specific scenario – which can be examined in further simulations taking the required specification into account.

The aging models themselves are available in an ever-increasing number of process design kits (PDK). Their development and parameterization are still very complex and often influenced by individual needs. Simplifications in the process should be sought to keep modeling efforts within reasonable limits.

In the future, simulation-based reliability analyses will provide designers with more information on the robustness of their designs. The aging models have to be designed to map the relevant effects without too much pessimism. If they manage this, IC designers can use simulation results to discuss reliability aspects efficiently with their customers without having to wait for elaborate and tedious tests. But the latter will still remain an inherent final component of IC development.