Embracing emerging approaches is essential for crafting packages that address the evolving demands of sustainability, technology, and consumer preferences.
Today’s heterogeneously integrated semiconductor packages represent a breakthrough technology that enables dramatic increases in bandwidth and performance with reduced power and cost compared to what can be currently achieved in traditional monolithic SoC designs.
Figure 1. A heterogeneously integrated device with 47 chiplets. (Image Source: Intel)
The evolving landscape of packaging design demands that designers and design teams adapt to a new and dynamic set of best practices, techniques, processes, and methodologies. Embracing these emerging approaches is essential for crafting packages that not only captivate consumers but also address the evolving demands of sustainability, technology, and consumer preferences.
By staying at the forefront of these innovations, designers can ensure that their creations are not only visually appealing but also functionally efficient and environmentally responsible, ultimately contributing to a more successful and sustainable future in the field of packaging design.
To efficiently design these new types of packages, designers and design teams need to embrace an emerging set of best practice design techniques, processes, and methodologies.
These best practices are defined as:
Package fabricators have strict metal fill requirements that address two main issues. First, the dielectric and metal layers can be very thin, 15 µm or less, and during the build-up and redistribution layer creation processes they can suffer from areas of delamination due to trapped pockets of gas. Second, uneven conductor densities on the same layer or across layer pairs can cause warpage in the package and/or the wafer. As a result, substrate fabricators do not like solid metal planes or large metal areas.
To avoid these issues, they typically provide rules, design rule checks, and often a design rule manual. The combination of these issues and all the rules makes the designer’s job of meeting the fabricators acceptance criteria a challenge. Further, the diversity of substrate technologies from numerous vendors means there’s no one-size-fits-all solution.
There are three methodologies that are typically used by designers to mitigate or control these issues:
Xpedition Package Designer has proven automated capabilities for all three methodologies. Understand how to use these capabilities efficiently and effectively to prevent extended design cycles or ECOs due to fabricator rejection of the design.
Figure 2. Hatched copper fill with additional automated degassing and wagon wheel pads.
Today, power requirements are continually increasing as more dies (or chiplets) are added to a package. The ability to analyze the core power characteristics and understand if there are enough vias and copper for the IC current requirements is essential to success. As multiple dies are integrated into a high-density heterogeneous package, not only must power be delivered through multiple rails, but the complexity of the current delivery path increases, as there are multiple dies in different locations pulling current from the rail.
Additionally, there is less room than there would be in a single monolithic package to connect supply voltage and current to the die. With these increased densities, there may not be enough copper to meet the design requirements of all the chiplets, which can result in additional layers in the package just to support the current requirements for all these different dies.
The recommended approach is to identify big DC-drop problems (rocks) early on to improve the end results. This procedure is not focused on seeking the highest level of accuracy for sign-off purposes. The “big rock” approach is basically allowing the designer to identify the possibility of a problem that they wouldn’t have seen otherwise, as early as possible, to avoid costly changes and delays. The designer starts by capturing some very basic information about the die or the components that are in the design.
Once the package designer has that basic information, Siemens Xpedition Package Designer software (xPD) makes it easy to fill in a current value for the voltage rail — all from within the tool. Analysis results from Siemens HyperLynx software are automatically annotated to xPD so users can clearly see that they’ve got a violation at a specific location where. The designer can then click on an error, automatically zoom to the area of the problem, fix it, and rerun the analysis.
HBM is a de facto standard for high-performance computing applications, such as CPUs, GPUs, and AI, but they are challenging to route in an efficient manner, in part because they have a 1,024-bit bus divided into channels, either 8 x 128 bit or 16 x 64 bit.
The challenges for the package designer fall into four broad areas:
Creating the complex via geometries for the fanout and breakout structures is the first step in implementing a channel. This is followed by routing the bits of the channel from the complex via breakouts on the logic die side to the breakouts on the HBM stack. Once this initial channel is completed and characterized for electrical compliance, it can then be considered good and ready for replication and reuse.
Meanwhile, it’s common that the compute chiplets, or SoC, will undergo refinement that impacts the die bump or pin assignments. When a part of an existing, replicated channel is modified and that change needs to be reflected to other channels, time-consuming ECOs will result — unless intelligent circuit replication is used. That’s where PhRC comes to the rescue. PhRC can yield a 25 percent total time saving over conventional cut-copy-paste, and this increases up to as much as 75 percent when combined with automated ECOs.
Figure 3. A complete HBM bus as a PhRC that can be intelligently replicated.
There is an old saying “many hands make light work” and this is especially true in package substrate design. Modern, heterogeneously integrated packages can be substantial in size, content, and complexity, making the process of ensuring design adherence to fabrication and assembly rules as well as achieving PPA and cost goals very challenging for a single designer.
Historically this challenge has been approached by using design shifts, especially useful when a company has geographically dispersed team. In theory, there can be three different designers, each working an eight-hour shift, to deliver continuous 24-hour design. But while this is good and may work for some companies, the expertise of only one designer can be applied at a time. And no one designer can be expected to be a master in every domain.
Fortunately, with concurrent team design, no one needs to be. Imagine having three to five different design domain experts working concurrently in real-time, each one focused on a particular design challenge that aligns with their expertise. Each designer can see what the others are doing and can even set up floorplan restriction areas to inform others not to focus on those areas. The result is a design environment that can multiply engineering resources and bring specialists into the picture concurrently. The result is a shorter design cycle, improved design quality and faster time to volume manufacture.
People often think of cut-copy-paste as physical design IP reuse, and at the most basic level it is, but it has severe limitations. It’s acceptable in some circumstances, but not for most, as it can be error-prone, requires manual netlist manipulation, and lacks traceability to the golden source data.
Most package designs contain areas of symmetry that are perfect for reuse — such as die-to-die routing of standard interfaces, core power and ground supply structures with complex via arrays, and device fanouts, among others. These physical design reuse circuits (PhRC) are native, first-class design objects that provide dynamic net propagation from the parent netlist, allow for rapid ECOs, and manage the golden source of verified design content. PhRCs drive modularity in design, require no netlist modifications, and offer a non-invasive ECO process. They are built using verified content, and their placement can be used across designs, designers, and teams.
Figure 4. Eight PhRC blocks of reusable fanout routing.
Semiconductor package test vehicles are commonly called daisy-chain design because the design is full of daisy-chain metal routing. Test vehicles have the physical characteristics of the actual target design, such as number of layers, and use the same parts. The daisy-chain routing of a test vehicle is used to test mechanical connections such as CTE and solderability, etc. Then physical structures such as materials, processes and design features are tested.
Finally copper structures such as heaters, serpentine, or offset vias are tested. Creating the test vehicle designs can be quite time consuming to design and visualize. The Daisy Chain Creator toolkit enables selection of chains across the interfaces of dies, packages, and PCBs. It provides the ability to easily color and name the chains. It also enables the creation of documentation for the technicians performing the tests.
Packages used to be just point-to-point redistribution connections between dies, micro-bumps, and the package’s BGA. There were some differential pairs, but overall, it was largely a “connect the dots” challenge.
The game has changed with the emergence of heterogeneously integrated chiplets, which are themselves disaggregated functions of what once would have been a monolithic SoC. A lot of data is passed between these chiplets, most of it at very high speeds using complex data bus protocols. Packages are now true, system interconnect platforms enabling the collection of compute chiplets and associated memory to meet the device architect’s intended goals.
Connectivity is no longer simply “connecting the dots,” in part because there are wide data buses, such as HBM and other protocols, connecting the compute chiplets. Datapath planning takes place during package floorplanning as chiplet placement is dependent on the interconnect datapaths to other chiplets and the external package pins. Designers can group interfaces or byte lanes into bundles and floorplan them to evaluate route real-estate and chiplet breakout strategies. Once these datapath plans are deemed to be viable scenarios, they can be annotated and forwarded to the actual physical design for detailed implementation.
Figure 5. Datapath planning and routing.
For more on the challenges and advantages of the exciting IC package technology and a fuller description of the seven best practices in IC package physical design, please check out the new eBook from Siemens EDA, IC package physical design best practices.
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