Thinking Digital To Design Analog, And Vice Versa

By Ed Sperling

Until several years ago, analog was a world apart from digital. Analog engineers could comfortably avoid many of the issues of Moore’s Law, viewing it as a costly bad habit with an equally bad outcome.

Most analog engineers gloated privately that they could still develop chips at 250nm, or at worst 130nm, while their digital counterparts were struggling to keep up with issues such as lithography, current leakage, new interconnects, different wafer sizes and new gate designs, just to name a handful. It also was before virtually all ASICs had morphed into systems on chip, which include both analog and digital.

Now the only question is whether those chips are mostly analog or mostly digital—which largely determines who’s in charge of the design team—but the design, simulation, layout and verification of these complex SoCs bring both worlds together into an unstable mixture.

On the tools side, companies are scrambling to bring these two worlds together into some sort of order. And while it may be particularly attractive to engineering managers, who are trying to get chip designs out the door in an ever-shortening time frame, it’s bringing yet another specialty into the design team—analog engineers, with a uniquely different way of looking at the world.

Graham Etchells, director of product marketing for Synopsys’ analog/mixed signal group, said there will never be full automation of the analog piece of the design, but there will at least be more automation. “Our goal is to put capabilities into the tools to make it easier to do things,” he said. “In the simulation and analysis environment, what we’ve done is allow a designer to set up simulations, run them, script all the measurements they want to do and view the results in a wave view analysis tool.”

Leading a horse to water…

Getting analog engineers to use the new tools is another matter, though.

“There’s a real dichotomy here,” Etchells said. “These guys are looking for ways to speed up what they do, but they don’t trust the automation and in some cases it doesn’t work. What we’ve been doing is putting capabilities into the tools that allows them to still control what’s going on, but it makes it easier for them to do things. In layout, for example, we added an autoconnect feature that allows you to snap your connection to pins or source drains or gates without having to zoom in and make sure the connection is exactly on the grid. We’ve also introduced an automatic bus command up to thousands of bits. Doing that by hand is a real pain.”

Virtually all of the major EDA vendors see a big need for continued analog tools development. Rajeev Madhavan, CEO of Magma Design Automation, said that mixed signal assembly is “cumbersome and error-prone.” In a keynote speech at ISQED, Mahdhavan said that everytime there is a handoff there are problems.

“The only way we’re handling this is with brute force,” he said. “As you get deeper into new geometries, the level of accuracy has to go to a new level of detail.”

He said that an unpredictable flow, which is common in mixed signal designs, can result in an 80% increase in engineering costs—and it gets worse. At 40nm and below, transistor currents can vary 30% to 50% and the difference between digital and mixed signal design re-spins is 1.2 versus 3 for mixed signal.

View from the trenches

But while most tools vendors see big promise and opportunity in the analog space, selling it to the engineers who will use those tools is another matter entirely. SoCs have created convergence among some varied groups that are changing the focus of those groups. David Smart, a fellow at Analog Devices, said the real shift is who’s in charge of the design team. In the converter space, for example, some of the product lines are now predominantly digital and run by digital engineers, while others are still predominantly analog with digital engineers working under their leadership.

For Smart, the real pain points in analog are narrow areas, which are not enough for the classic EDA tools vendors to make significant investments. Also important and ripe for general improvements are areas such as simulation and place-and-route.

“Place and route inside of analog cells has not caught on well,” he said. “Layout is labor-intensive and it limits how many times you can change the design. Right now we try to get it pretty close to perfect on the first pass. If you come to the end and the interconnect line is too long and to fix it you have to shuffle all this stuff around, you can’t just push a button. From an intellectual standpoint, automating all of this is very appealing, but there’s nothing around. Still, it would be good to have tools so you’re not surprised with the results.”

Smart also said that the reason many EDA tools have not been accepted by engineers is that they usually don’t work as well as someone who is an expert at analog design. “We’ve seen a lot of attempts, but the tools are usually not superior to what an analog expert can do.” He noted that Analog Devices frequently teams seasoned experts with young engineers skilled in the newest tools and arrives at a better result than just relying on automated design.

It’s currently not possible, for example, to automate verification on multiple analog circuits because each circuit is different. Simulations sometimes take weeks, which is another area where improvements are needed. SPICE has progressed to Fast SPICE for big circuits, which was regarded by analog engineers as inaccurate, to Accurate Fast SPICE. But for most engineers, it’s still too slow. 

Tools vendors are committed to making a dent in this space, however, in large part because analog is no longer a separate world. In the future, there likely will be applications engineers and business people, who will make quick decisions about build vs. buy, marketers (who traditionally have stood on the sidelines even though they have enormous influence over the feature sets in chips) and software application writers, who at least will be involved in establishing the proper programming interfaces. What a difference a process node makes.