Using data to target areas on a chip where defects are most likely to occur.
Increasing complexity at advanced nodes makes it much harder to locate defects and latent defects because there is more surface area to cover and much less space between the various components in a leading-edge chip design. Ron Press, technology enablement director at Siemens Digital Industries Software, talks about why it’s so important to predict where defects are most likely to occur in these designs, and how to optimize test patterns to be able to quickly target those areas with tests.
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