This software-programmable, heterogeneous compute platform combines scalar engines, adaptable engines, and intelligent engines to achieve performance improvements over the fastest FPGA implementations and over 100X over today’s fastest CPU implementations — for data center, wired network, 5G wireless, and automotive driver assist applications.
Recent technical challenges have forced the industry to explore options beyond the conventional “one size fits all” CPU scalar processing solution. Very large vector processing (DSP, GPU) solves some problems, but it runs into traditional scaling challenges due to inflexible, inefficient memory bandwidth usage. Traditional FPGA solutions provide programmable memory hierarchy, but the traditional hardware development flow has been a barrier to broad, high-volume adoption in application spaces like the Data Center market.
The solution combines all three elements with a new tool flow that offers a variety of different abstractions — from framework to C to RTL-level coding — into an adaptive compute acceleration platform (ACAP). This new category of devices, Xilinx’s Versal ACAPs, allows users to customize their own domain-specific architecture (DSA) from these three programmable elements.
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AMD CTO Mark Papermaster talks about why heterogeneous architectures will be needed to achieve improvements in PPA.
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