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Vertical MoS2 transistors with sub-1-nm gate lengths

Side-wall MoS2 transistors with an atomically thin channel and a physical gate length of sub-1 nm using the edge of a graphene layer as the gate electrode

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Abstract

“Ultra-scaled transistors are of interest in the development of next-generation electronic devices. Although atomically thin molybdenum disulfide (MoS2) transistors have been reported, the fabrication of devices with gate lengths below 1 nm has been challenging. Here we demonstrate side-wall MoS2 transistors with an atomically thin channel and a physical gate length of sub-1 nm using the edge of a graphene layer as the gate electrode. The approach uses large-area graphene and MoS2 films grown by chemical vapour deposition for the fabrication of side-wall transistors on a 2-inch wafer. These devices have On/Off ratios up to 1.02 × 105 and subthreshold swing values down to 117 mV dec-1. Simulation results indicate that the MoS2 side-wall effective channel length approaches 0.34 nm in the On state and 4.54 nm in the Off state. This work can promote Moore’s law of the scaling down of transistors for next-generation electronics.”

Find the technical paper link here. Published Mar. 2022.

Wu, F., Tian, H., Shen, Y. et al. Vertical MoS2 transistors with sub-1-nm gate lengths. Nature 603, 259–264 (2022). https://doi.org/10.1038/s41586-021-04323-3.

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