Week In Review: Design, Low Power

Arm announced a new processor targeted at autonomous driving applications. The Cortex-A76AE is a superscalar, out-of-order processor that incorporates Split-Lock safety technology. Split-Lock allows CPU clusters in an a SoC to be configured either in ‘split mode’ for high performance, allowing two (or four) independent CPUs in the cluster to be used for diverse tasks and applications, or ‘lock mode’ where CPUs are in lock-step, creating one (or two) pairs of locked CPUs in a cluster, for higher safety integrity applications. It is optimized for 7nm process nodes.

A new process design kit based on SMART Photonics’ Indium Phosphide (InP) process is now available in Synopsys’ OptSim Circuit tool to support InP-based photonic integrated circuit (PIC) design and simulation. The addition allows users to use the PIC Design Suite to schematically capture and simulate InP-based PIC designs with the SMART PDK building blocks, and then synthesize and verify a SMART-foundry-compatible layout.

sureCore launched a low-power SRAM IP application-centric customization service focused on specific requirements for wearable, wireless, augmented reality and IoT devices. The new service prioritizes power optimization over speed and area and covers a spectrum of memory requirements including multiple read/write ports, ultra-low leakage retention modes, low dynamic power, near-threshold operation, write masking and BIST/DFT support.

The average SoC design cost will only increase 1.7% to $5.3 million by 2023, according to Semico Research. This is partly driven by the number of designs staying at older nodes, notes Rich Wawrzyniak, Sr. Market Analyst for ASIC & SoC at Semico. “For each of the three types of SoC there is still considerable activity at the older nodes of 90nm, 65nm and 40nm. Costs at these geometries are much less than at 10nm and 7nm so even though these newer designs cost much more, the average for all SoCs has dropped due to the increase in new designs for Basic SoC.” However, design costs at the 7nm node for an Advanced Performance Multicore SoC first-time effort are projected to be 23% higher than at the 10nm node.

Synopsys debuted the latest releases of the LucidShape CAA V5 Based and LucidDrive software products for automotive lighting analysis and simulation, which offer new features to support faster design cycles, lower development costs, and enhanced realism of headlight simulations.

Boeing licensed Flex Logix’s EFLX4K Logic and DSP embedded FPGA cores on GlobalFoundries’ 14nm process. The EFLX4K Logic IP core has 4K 4-input-equivalent-LUTs, 632 inputs and 632 outputs and is a complete eFPGA. The EFLX4K DSP IP core replaces about ¼ of the LUTs with 40 multiplier-accumulators for DSP and AI applications.

Events
Digital Marketing Workshop 2.0: Oct. 3, 6 p.m. – 8:30 p.m. in Milpitas, CA. A workshop focused on three organizational shifts that are key to mastering digitally-driven marketing and sales and conducting marketing in an agile manner.

Arm TechCon: Oct. 16-18 in San Jose, CA. The Arm-centric conference and expo will feature keynotes by senior Arm executives as well as best-practices for implementing Arm IP in a range of designs, including IoT and automotive. The company has also teased an expanded roadmap for future products to be released at the show.

RISC-V Summit: Dec. 3-6 in Santa Clara, CA. The first annual conference and exhibition dedicated to the RSIC-V ISA ecosystem. Training sessions, workshops, and presentations will be available, followed by a day for Foundation members.