Week In Review: Design, Low Power

M&A
Synopsys acquired Moortec, a provider of in-chip monitoring technology specializing in process, voltage and temperature (PVT) sensors. Moortec’s sensors will be a key component to Synopsys’ new Silicon Lifecycle Management (SLM) platform. “This acquisition accelerates the expansion of our SLM platform by providing our customers with a comprehensive data-analytics-driven solution for devices at the most advanced process nodes,” said Sassine Ghazi, COO of Synopsys. Moortec is based in Plymouth, UK, and was founded in 2005. Terms of the deal were not disclosed.

Silvaco acquired the memory compiler technology and standard cell libraries of Dolphin Design. Dolphin Design provides ultra-low power, high-density memory compilers, including ROM, SRAM, and Register File compilers. It also provides other IP including power management, audio, and body bias IP, platform solutions, and design services. Formerly named Dolphin Integration, the company’s assets were acquired jointly in 2018 by materials provider Soitec and defense manufacturer MBDA. Founded in 1985, Dolphin is based in Meylan, France.

IP
Imagination Technologies uncorked IMG Series4, a neural network accelerator for ADAS and autonomous driving. Its multi-core architecture is designed to run full network inferencing while meeting functional safety and low power requirements. Available in configurations of 2, 4, 6, or 8 cores per cluster, it provides 12.5 TOPS per core at less than one watt and splits input data tensors into multiple tiles for efficient data processing and improved bandwidth efficiency.

CAST debuted a new IP core that implements a slave controller for the MIPI I3C BasicSM interconnection bus. The I3C-S MIPI I3C Basic Slave Controller core supports the latest I3C Basic specification, is suitable for any I3C bus topology, and includes an I3C to AMBA AHB bridging mode.

Standards
The CXL Consortium published the CXL 2.0 specification. The open industry-standard interconnect provides coherency and memory semantics using high-bandwidth, low-latency connectivity between host processor and devices. The CXL 2.0 specification adds support for switching for fan-out to connect to more devices; memory pooling for increased memory utilization efficiency and providing memory capacity on demand; and support for persistent memory. It is backwards compatible with CXL 1.1 and 1.0.

Synopsys debuted verification IP for Compute Express Link (CXL) 2.0 designed for performance in data-intensive SoCs. The VIP uses a UVM architecture, is integrated with Synopsys Verdi Protocol and Performance Analyzer, and includes built-in coverage and verification plans.

PLDA added CXL 2.0 support for its XpressLINK and XpressLINK-SOC CXL IP solutions.

Cadence’s Tensilica ConnX B10 and ConnX B20 DSPs received Automotive Safety Integrity Level B in support of D (ASIL B(D))-compliant certification from SGS-TÜV Saar, which includes support for both random hardware faults and systematic faults. The DSPs are optimized for automotive radar, lidar and V2X applications.

Global
What will be the impact of the U.S. presidential election on trade relations with China? In two reports from Reuters, analysts expect restrictions on companies like Huawei to continue, with tech companies lobbying to loosen controls countered by expected congressional pushback. Regardless of the stance taken by the Biden administration, China is already on a path to strengthen its semiconductor capabilities, said Fang Xingdong, director of the Consortium of Internet and Society at the Communication University of Zhejiang: “in the high-tech field, competition and game theory will not end, and China and the U.S. will compete with each other with true innovation capabilities in the next decade.”

Accounting firm KPMG also sees China’s semiconductor industry growing, according to South China Morning Post. Jamie Li, partner at KPMG’s integrated chips intelligence industry group in Shanghai, said that “the Covid-19 pandemic has spurred market demand for 5G chips, memory chips and logic semiconductor products,” and expects “sound and continuous” growth even in the face of U.S. sanctions.

Meanwhile, Huawei has inked a $15.2 billion deal to sell its Honor budget smartphone brand to handset distributor Digital China and the government of Shenzhen, according to reports.

Deals
Vidatronic used Cadence’s Spectre X Simulator for electromigration and IR drop reliability analysis on leading-edge 7nm and 5nm analog IP designs for mobile, hyperscale and other consumer electronics. Vidatronic cited up to 10X speedup and a 3X reduction in memory consumption versus the previous-generation Spectre simulator.

Graphcore utilized a range of Mentor products to design and verify its latest M2000 platform based on the Graphcore Colossus GC200 Intelligence Processing Unit (IPU) processor. Tools used include Caliber physical and circuit verification, PCIe 4.0 VIP, Tessent for DFT, and several others for power and thermal management and PCB design. Graphcore cited the comprehensive portfolio of tools as well as performance and capacity.

L&T Technology Services Limited (LTTS) adopted Cadence’s Clarity 3D Solver to analyze complex high-speed interconnects, including both 10G and 25G Ethernet and MIPI signals, for its mobile camera and memory devices. LTTS cited the ability to conduct multiple iterations per day and shorten design cycle time by three weeks.

Numbers
Ansys reported third quarter 2020 financial results with revenue of $367 million, up 7% from the third quarter last year. On a GAAP basis, earnings per share in Q3 2020 were $0.87, down 16% from $1.04 in Q3 2019, while non-GAAP earnings were $1.36 per share, down 4% from $1.42 per share in the same quarter last year. CEO Ajei Gopal called out double digit growth in Japan and South Korea as well as robust spending from the aerospace and defense sector.

Events
Find a new conference or learning opportunity at our events page, or check out an upcoming webinar.

Currently happening is the WE20: Conference For Women Engineers on Nov. 2-30 and the SC20: International Conference For HPC, Networking, Storage & Analysis on Nov. 9-19. Coming up, the Intelligent Edge Conference will take place Nov. 17-18 while the FPGA Hackathon will be held Nov. 20-22.