Week In Review: Design, Low Power

Synopsys acquires yield management biz; RF design tool interoperability; RISC-V cores; ML FPGA optimization.


Synopsys will acquire the semiconductor and flat panel display solutions of BISTel. The acquisition will add an integrated and comprehensive yield management and prediction solution for manufacturing quality and efficiency. BISTel provides engineering equipment systems and AI applications for smart manufacturing in a range of industries. “Combining Synopsys’ and BISTel’s expertise in fab solutions will enable us to bring to market innovative process control products that help our customers maximize their economic opportunity,” said Howard Ko, general manager of the Silicon Engineering Group at Synopsys. Terms of the deal were not disclosed; it is expected to close in Synopsys’ fiscal Q4 2021.

Cadence debuted the latest version of its RF tool, AWR Design Environment Version 16. AWR V16 adds cross-platform interoperability to support RF to mmWave IP integration for heterogeneous technology development across the Virtuoso design platform and the Allegro PCB and IC package design platforms, as well as integration with Clarity 3D Solver and Celsius Thermal Solver. Finite-element analysis (FEA) solver performance was also improved.

SEGGER’s J-Link debug probes and Embedded Studio IDE now fully support Codasip’s RISC-V processors. J-Link, using the Open Flashloader concept, allows programming of flash memories connected to devices using Codasip RISC-V cores, while Embedded Studio’s Linker and Runtime Libraries aim to minimize code size.

Samsung’s System LSI Business deployed Synopsys’ PrimeShield design robustness solution on its advanced process technologies for next-generation designs spanning mobile, 5G, and automotive applications. PrimeShield provides voltage slack, design variation and global skew analysis. Samsung cited the tool’s ability to address variation challenges and deliver quality-of-results advantages.

Presto Engineering adopted Cadence’s system design and analysis portfolio for advanced IC packaging to design IC packaging solutions for its automotive and IoT customers. Presto cited improved turnaround time and additionally plans to provide Cadence with input on software features, functions, and workflows specific to end customer and market needs.

Automotive component supplier DENSO selected Siemens’ Simcenter portfolio of simulation and test applications for model-based development processes.

Defense company Meggitt adopted Ansys simulation solutions as its common modeling platform for development of safety-critical aircraft components, including thermal management systems.

Codasip unveiled A71X, a RISC-V-based 64-bit core aimed at the application domain and able to run Linux. A superscalar core, it is able to process instructions from one thread in two different execution units. Configurations will include all microarchitectures that have already been announced for the earlier Codasip A70X, including support for the RISC-V P extension and multi-core features. “The new dual-issue capability will allow for a jump in performance without significant increase in power and area, which will make it possible to serve a much wider range of applications,” said Codasip CTO Zdeněk Přikryl. It will be available toward the end of 2021.

Arm released details of its Confidential Compute Architecture (Arm CCA), a feature in Armv9-A that enables supervisor software, such as kernels or hypervisors, to manage an application’s resources without having the right to access them. Based around a confidential computing environment called a Realm, it can protect data and code while in use. A new data structure, the Granule Protection Table, tracks whether a page is to be used for Realms, TrustZone, or for the normal world, and checks if every access is permitted.

SiFive uncorked a new family of RISC-V processors. The first two cores released are the P270, a Linux capable processor with full support for the RISC-V vector extension v1.0 rc, and the P550, which the company says is its highest performance to date with a SPECInt 2006 score of 8.65/GHz. Intel will offer the P550 on its 7nm Horse Creek platform, said Amber Huffman, Intel Fellow and CTO of IP engineering group at Intel. “By combining Intel’s leading-edge interface IP such as DDR and PCIe with SiFive’s highest performance processor, Horse Creek will provide a valuable and expandable development vehicle for cutting-edge RISC-V applications.”

Xilinx introduced Vivado ML Editions, an FPGA EDA tool suite based on ML optimization algorithms with advanced team-based design flows. The tool includes ML-based logic optimization, delay estimation and intelligent design runs, which automates strategies to reduce timing closure iterations. It also adds the concept of an Abstract Shell, which allows users to define multiple modules within the system to be compiled incrementally and in parallel. It also can hide IP design details outside of the modules. The company said Vivado ML Editions delivers 5x faster compile time and QoR improvements on average 10% for complex designs, compared to the current Vivado HLx Editions.

Socionext licensed Flex Logix’s EFLX 4K eFPGA for use in a 7nm ASIC being developed for a major communication company’s 5G platform. Socionext said it was able to eliminate one chip in the base station, and that the reprogrammable ASIC can be reconfigured after tape-out to adapt to new requirements and changing standards and protocols as needed.

Lattice Semiconductor launched its CertusPro-NX general purpose FPGA family. The FPGAs focus on power efficiency and support up to eight programmable SERDES lanes capable of speeds up to 10.3 Gbps, LPDDR4 external memory, and up to 100k logic cells in a design footprint of 81 mm2.

Connectivity & sensors
TomTom used Infineon’s AIROC CYW43455 Wi-Fi and Bluetooth combo chip to add wireless connectivity in its TomTom GO Discover satnav, enabling it to download map updates quickly and connect to smartphones.

CEVA introduced RivieraWaves UWB, a power-efficient ultra-wideband (UWB) turnkey MAC and PHY platform IP compliant with the IEEE 802.15.4z standard and in accordance with the FiRa consortium specifications. The IP provides secure, centimeter-level accuracy and robust location information through Time-of-Flight ranging and Angle-of-Arrival processing.

Infineon, pmdtechnologies, and ArcSoft are teaming up on a Time-of-Flight camera that can work under the display of commercial smartphones. The sensor will provide high-quality infrared images and 3D data for security-related applications like face authentication and mobile payment.

Jim Hogan, executive, angel investor and board member, and Stanford University Professor Edward J. McCluskey were named honorees in the Kaufman Hall of Fame, which posthumously recognizes contributions to the electronic system design industry.

Upcoming Webinars
Ansys is hosting a live webinar on clock jitter on Tuesday, June 29, for North America and Europe, and Thursday, July 1, in Asia. The focus is on accurate modeling of dynamic voltage drop, and how to spot violations quickly.

Siemens is hosting an on-demand webinar on chip development and lifecycle strategies, which looks at improvement in key process capabilities, technology support, and best practices in fabs, fabless, IDMs, foundries, and OSATs or subcons.

Find more upcoming chip industry events here.

Leave a Reply

(Note: This name will be displayed publicly)