Week In Review: Design, Low Power

Intel released Tunnel Falls, its newest quantum research chip, to quantum computing researchers interested in using the 12-qubit silicon chip for their own experiments and research.  Intel is also providing the chips to research laboratories, with help from LQC (LPS Qubit Collaboratory) through the Army Research Office. The first labs to receive the chip are LPS, Sandia National Laboratories, the University of Rochester, and the University of Wisconsin-Madison. Tunnel Falls is a spin qubit device fabricated on 300-millimeter wafers in the D1 fabrication facility, using extreme ultraviolet lithography (EUV) and gate and contact processing techniques. Each qubit device is essentially a single electron transistor, said Intel.

AMD unveiled its AI generative platform with an accelerator family, the AMD Instinct MI300 Series, with the MI300X sampling to AMD’s key customers in Q3. It can fit large language models because of its large memory. Based on the next-gen AMD CDNA 3 accelerator architecture, the MI300X has up to 192 GB of HBM3 memory for compute and memory efficiency needed for large language model training and inference for generative AI workloads, according to AMD’s press release. AMD also revealed its 4th generation AMD EPYC processors for high-performance computing (HPC), cloud, and enterprise server workloads. The processor portfolio has a 4th “Zen 4c” core architecture, the AMD EPYC 97X4 cloud native-optimized data center CPUs to deliver the thread density. The 4th Gen has Amazon Elastic Compute Cloud (Amazon EC2) M7a instances for Amazon Web Services (AWS). The EC2 M7a instances offer additional processor capabilities of AVX3-512, VNNI, and BFloat16, along with 50% more computing performance over the M6a instances, according to Amazon in a press release.

Design

Cadence and Samsung Foundry have signed a multi-year agreement to expand its design IP portfolio to cover Samsung Foundry’s SF5A process technology. The agreement also includes the latest DDR5 8400+ and GDDR7 solutions on Samsung Foundry’s advanced SF3 technology, for designers wanting a high-performance, high-bandwidth memory interface tool for designing generative AI/ML, hyperscale, and high-performance computing (HPC) applications.

Synopsys and Samsung also announced an expanded agreement to develop IP to reduce design risk and accelerate silicon success for automotive, mobile, HPC, and multi-die designs. Synopsys will optimize IP to meet Grade 1 or Grade 2 temperature and AEC-Q100 reliability requirements for Samsung’s SF5A and SF4A automotive process nodes. The auto-grade IP for ADAS SoCs will include design failure mode and effect analysis (DFMEA) reports that can save months of development effort for automotive SoC applications. Synopsys already has an agreement in place with Samsung to enhance the Synopsys IP offering for Samsung’s advanced 8LPU, SF5, SF4 and SF3 processes and includes Foundation IP, USB, PCI Express, 112G Ethernet, UCIe, LPDDR, DDR, MIPI, among others.

Rolls-Royce is using Intel’s HPC with Ansys’ multiphysics simulation tools to shorten the time it takes to run a thermo-mechanical model of Rolls-Royce’s gas-turbine engine. The time now clocks in at less than 10 hours to simulate the model, an improvement over the more than 1,000 hours it used to take. Computing resources at the Oak Ridge Leadership Computing Facility, HPE, and researchers at the NCSA (National Center for Supercomputing Applications) supported the work.

For embedded systems developers, Infineon just released its ModusToolbox 3.1 a new dashboard that incorporates training and workflow guides. The toolbox is for Infineon products and works with different integrated development environments (IDEs).

Sharing of data in design and manufacturing is a big problem. A lot of critical data comes out of the fab. How does it move through an organization so it can be shared with the chip architect and other parts of the design-through-manufacturing chain? Read what the CEOs of large EDA, IP, and test companies said.

Siemens is speeding up its NX software, in Xcelerator, with a GPU that runs a new Performance Predictor capability, delivering near real-time simulation results.

Stoneridge, Inc., a Michigan-based automotive electronics design company, is adopting Siemens Xcelerator portfolio.

Read the latest design and verification tech papers:

• An Energy Efficient, Linux-Capable RISC-V Host Platform Designed For The Seamless Plug-In And Control Of Domain-Specific Accelerators
• Chiplets: Bridging The Gap Between The System Requirements And Design Aggregation, Planning, And Optimization
• Tools For Co-Designing HPC Systems Using RISC-V As A Demonstrator

Products & deals

Infineon’s new ISOFACE dual-channel digital isolators for high-voltage isolation, uses Infineon’s coreless transformer isolation technology with improved common-mode transient immunity (CMTI), in a narrow-body DSO-8 package, to transfer electrical signals from one PCB to another. The devices support data rates of up to 40 Mbps and can maintain its signal integrity over a wide operating temperature range and across the production spread, says the company in a press release. ISOFACE devices are pin-to-pin compatible with other suppliers’ products. The isolators will be used in servers, telecom and industrial SMPS, industrial automation systems, motor control and drives, energy storage systems, and solar inverters.

Infineon also announced its next 1200 V CoolSiC Trench MOSFET in TO263-7 package that Infineon says has 25% lower switching losses compared with its first generation. It is an automotive-graded silicon carbide (SiC) MOSFET with high power density and efficiency for bi-directional charging. The gate-source threshold voltage (V GS(th)) is greater than 4 V and the Crss/ Ciss ratio is very low. The reliable turn-off at V GS = 0 V helps avoid parasitic turnings-on. The SiC MOSFET junction temperature is also lower by 25% compared with the first generation. KOSTAL is already using the CoolSiC MOSFET in their OBC platform. More details are available.

Siemens Digital Industries Software added the Supplyframe Design-to-Source Intelligence platform into the Siemens Xcelerator portfolio.

Winbond introduced its 8Mb 3V NOR W25Q80RV, the initial offering in a new portfolio of high performance, small form-factor serial flash devices for edge applications that need a higher read performance. Operating on a single 2.7V to 3.6V power supply, the devices have power-down current down to 1μA. Winbond makes the chip at its own 12-inch wafer fab on 58nm technology. The company said the chip was smaller than a 90nm technology version.

Power and performance

Movellus announced an integrated droop response system that detects and responds to voltage droops, has extensive monitoring and observability features, and makes it possible for fine-grained dynamic voltage and frequency scaling (DVFS). The system has APB and JTAG interfaces for silicon health and analytics management at bringup, production test, and in-field. The Aeonic Generate AWM2 is now sampling with some of Movellus’ customers. AWM2 is as off-the-shelf synthesizable IP.

Rather than simply shrinking all circuit dimensions, new device architectures must balance these factors to optimize overall circuit performance. As transistors continue to shrink, the minimum separation between them is becoming a critically important obstacle to further increases in device density. The sequential CFET approach seems to have a lot to recommend it.

Read the latest power and performance tech papers:

• SB MOSFET-Based Ultra-Low Power Real-Time Neurons For Neuromorphic Computing (Indian Institute Of Technology)
• An Energy Efficient, Linux-Capable RISC-V Host Platform Designed For The Seamless Plug-In And Control Of Domain-Specific Accelerators
• Chiplets: Bridging The Gap Between The System Requirements And Design Aggregation, Planning, And Optimization
• Tools For Co-Designing HPC Systems Using RISC-V As A Demonstrator
• A Step Towards Eliminating The Von-Neumann Bottleneck By Co-Locating Photonic Computing Elements And Non-Volatile Memory
• Object Detection CNN Suitable For Edge Processors With Limited Memory

Read the latest quantum computing tech papers:

• Metallic Behaviour Of Semiconducting Colloidal Quantum Dots (RIKEN, Others)
• End-To-End System Architecture For Quantum RAM (Yale, AWS, Caltech)

Upcoming events

• ISCA 2023: International Symposium on Computer Architecture, Orlando, FL, June 17 – 21
• EMLC 2023: European Mask and Lithography Conference, Dresden, Germany, June 19 – 21
• Keysight World, various locations, June 20 – 23
• Supply Chain Forum, Frankfurt, Germany, June 21
• Leti Innovation Days, June 27 – 29
• Samsung Foundry Forum & SAFE Forum 2023, San Jose, CA, June 27 – 28
• SEMICON China, Shanghai, China, June 29 – July 1
• MIPI DevCon 2023: Mobile and Beyond, San Jose, CA, June 30
• DAC 2023- Design Automation Conference, San Francisco, CA, July 9 – 13
• SEMICON West 2023, San Francisco, CA, July 11 – 13
• Rambus Design Summit, July 18 – 19

Further reading

Check out the latest Low Power-High Performance and Systems & Design newsletters for these highlights and more:

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