Week In Review: Design, Low Power

Synopsys’ board of directors appointed Sassine Ghazi as president and chief executive officer effective on Jan. 1, 2024. Ghazi, who is currently the COO, will succeed Aart de Geus, co-founder, chair, and CEO of Synopsys, who will then become the executive chair of board of directors.

IBM Research introduced  an energy-efficient mixed-signal analog AI chip for DNN inferencing and demonstrated how to “seamlessly combine analog in-memory computing with several digital processing units and a digital communication fabric.”

Safety is an increasing concern across many industries, but standards and methods are not in place to ensure electronic systems attain a defined level of safety over time. Much of the initial standardization is falling on the shoulders of the chip industry, which provides the underlying technology, and it raises questions about what more can be done to improve safety.

University of Colorado Boulder will lead a multi-university research team to address thermal challenges in electronics, with funding from DARPA.  The team will start by “creating computational thermal model of individual transistors at the deeply scaled nanometer level, one millionth of a millimeter in size, and will then expand the model to a millimeter-scale circuit element with 300,000 transistors.”

Deals and Products

Intel and Synopsys expanded their long-standing IP and EDA partnership, allowing IP access for the Intel Foundry ecosystem.

Intel terminated its February 2022 agreement to acquire Tower Semiconductor, an Israeli-based analog semiconductor foundry, because Intel says it could not obtain regulatory approvals by the deadline.

OpenHW Group announced a development kit is now available to order, including an open-source RISC-based PCB which integrates OpenHW’s CORE-V MCU and various peripherals, a software development kit with a Eclipse-based integrated development environment, as well as connectivity to Amazon Web Services.

Alphawave Semi recently announced its successful 3nm tapeouts of HBM3 and UCIe IP for chiplets aimed at generative AI and data center workloads.

Data Centers

Tesla appears to be getting into the data center business, based on job postings for engineering staff to design and oversee construction of Tesla Data Centers.

With so much at stake in chip design today, experts from AMD, Siemens EDA, Cadence, Synopsys, and Lightmatter discuss achieving the best ROI with cloud resources and which companies are using the cloud and why.

The South Korean government plans to fund some data center projects made with domestic AI chips, among other tech projects meant to spur in-country electronics and semiconductor industry.

AI is forcing fundamental shifts in chips used in data centers and in the tools used to design them, but it also is creating gaps between the speed at which that technology advances and the demands from customers.

Quantum

Los Alamos National Lab researchers proposed a new strategy to quantum computing hardware that “implements an algorithm in natural quantum interactions to process a variety of real-world problems faster than classical computers or conventional gate-based quantum computers can.”

Researchers working at the University of Cambridge used light as a switch to control the spin of electrons at room temperature. The team was able to make electrons behave like tiny magnets, connecting them with a bridge and shining a light on them to make the spinning electrons spin in tandem. Once the bridge is removed, the electrons are still linked.

U.S.’ National Institute of Standards and Technology (NIST) successfully demonstrated its new standard for measuring ultra-low pressures, which will be useful in measuring the remaining particles in a vacuum by the pressure they exert. Chip manufacturing, gravitational wave detectors, and quantum computers could benefit. The cold atom vacuum standard (CAVS) can reliably measure the much lower vacuum pressures — a trillionth of the Earth’s sea-level atmospheric pressure and below.

Research and technical papers

Read the latest design and verification tech papers:

• New Architecture Elements For 5G RF Front-End Modules To Reduce Noise, Improve Efficiency, And Allow Multiple Radio Transmitters
• Modification Of An Existing E-Graph Based RTL Optimization Tool As A Formal Verification Assistant
• A Safety Island For Safe Use Of HPC Devices For Safety-Critical Systems With RISC-V

Read the latest power and performance tech papers:

• Modeling Optical Loss And Crosstalk Noise For Silicon-Photonic-Based Neural Networks Of Different Scales
• A Search Framework That Optimizes Hybrid-Device IMC Architectures For DNNs, Using Chiplets
• New & Faster Single-Crystalline Oxide Thin Films (Max Planck, Cambridge, U Of Penn.)
• How Attackers Can Read Data From CPU’s Memory By Analyzing Energy Consumption

Read the latest optoelectronics and photonics tech papers:

• How Band Nesting Can Achieve Near-Perfect Optical Absorption In Just Two Layers Of TMD Materials
• Performance Enhancement Of An Si Photodetector By Incorporating Photon-Trapping Surface Structures
• Automotive Lidar: Softening The Trade-Off Between Ambiguity Range And Speed

Upcoming Events

Find upcoming chip industry events here, including:

• SPIE Optics + Photonics 2023 — August 20 – 24 (San Diego, CA)
• DARPA: Electronics Resurgence Initiative (ERI) — August 22 – 24 (Seattle, WA)
• Hot Chips 2023 — August 27 – 29 (Hybrid/Stanford University)
• NVMTS 2023: Non-Volatile Memory Technology Symposium — August 30 – September 1 (Leuven, Belgium)
• IEEE International System-on-Chip Conference (SOCC): SoCs/ SiPs for Edge Intelligence & Accelerated Computing — September 5 – 8 (Santa Clara, CA)

Further reading

Check out the latest Low Power-High Performance and Systems & Design newsletters for these highlights and more:

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